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february 2001 1 ? 2001 actel corporation 3.0 integrator series fpgas: 1200xl and 3200dx families features high capacity ? 2,500 to 30,000 logic gates up to 3kbits configurable dual-port sram fast wide-decode circuitry up to 250 user-programmable i/o pins high performance 225 mhz performance 5 ns dual-port sram access 100 mhz fifos 7.5 ns 35-bit address decode ease-of-integration synthesis-friendly architecture supports asic design methodologies. 95?100% device utilization using automatic place-and-route tools. deterministic, user-controllable timing via timing driven software tools with up to 100% pin fixing. ieee standard 1149.1 (jtag) boundary scan testing. general description actel?s integrator series fpgas are the first programmable logic devices optimized for high-speed system logic integration. based on actel?s proprietary antifuse technology and 0.6-micron double metal cmos process, integrator series devices offer a fine-grained, register-rich architecture with embedded dual-port sram and wide-decode circuitry. integrator series? 3200dx and 1200xl families were designed to integrate system logic which is typically implemented in multiple cplds, pals, and fpgas. these devices provide the features and performance required for today?s complex, high-speed digital logic systems. the 3200dx family offers fast dual-port sram for implementing fifos, lifos, and temporary data storage. the large number of storage elements can efficiently address applications requiring wide datapath manipulation and transformation functions such as telecommunications, networking, and dsp. integrator series product profile family 1200xl 3200dx device a1225xl a1240xl a1280xl a3265dx a32100dx a32140dx a32200dx a32300dx capacity logic gates 1 sram bits 2,500 n/a 4,000 n/a 8,000 n/a 6,500 n/a 10,000 2,048 14,000 n/a 20,000 2,560 30,000 3,072 logic modules sequential combinatorial decode 231 220 n/a 348 336 n/a 624 608 n/a 510 475 20 700 662 20 954 912 24 1,230 1,184 24 1,888 1,833 28 sram modules (64x4 or 32x8) n/a n/a n/a n/a 8 n/a 10 12 dedicated flip-flops 231 348 624 510 700 954 1,230 1,888 clocks 22226266 user i/o (maximum) 83 104 140 126 152 176 202 250 jtag no no no no yes yes yes yes packages pl84 pq100 vq100 pg100 pl84 pq100 pq144 tq176 pg132 pl84 pq160 pq208 tq176 pg176 cq172 pl84 pq100 pq160 tq176 pl84 pq160 pq208 tq176 cq84 pl84 pq160 pq208 tq176 cq256 pq208 rq208 rq240 cq208 cq256 rq208 rq240 cq256 note: logic gate capacity does not include sram bits as logic. v3.0
integrator series fpgas: 1200xl and 3200dx families 2v3.0 ordering information application (temperature range) c = commercial (0 to +70c) i = industrial (?40 to +85c) m = military (?55 to +125c) b=mil-std-883 package type cq = ceramic quad flat pack pg = ceramic pin grid array pl = plastic leaded chip carrier pq = plastic quad flat pack rq = plastic power quad flat pack tq = thin (1.4 mm) quad flat pack vq = very thin (1.0 mm) quad flat pack speed grade blank = standard speed 1 = approximately 15% faster than standard 2 = approximately 25% faster than standard 3 = approximately 35% faster than standard f = approximately 30% slower than standard part number a1225 = 2500 gates a1240 = 4000 gates a3265 = 6500 gates a1280 = 8000 gates a32100 = 10000 gates a32140 = 14000 gates a32200 = 20000 gates a32300 = 30000 gates die revision xl = 1200xl family dx = 3200dx family package lead count a1225 ? pq 100 c xl operating voltage v = 3.3 volt blank = 5.0 volt v
v3.0 3 integrator series fpgas: 1200xl and 3200dx families product plan speed grade* application ? fstd ? 1 ? 2 ? 3cimb a1225xl device 84-pin plastic leaded chip carrier (plcc) ???? ? ?? ?? 100-pin plastic quad flat pack (pqfp) ???? ? ?? ?? 100-pin very thin plastic quad flat pack (vqfp) ???? ? ?? ?? 100-pin ceramic pin grid array (cpga) ? ??? ? ? ??? a1225xlv device 84-pin plastic leaded chip carrier (plcc) ? ? ??? ? ??? 100-pin very thin plastic quad flat pack (vqfp) ? ? ??? ? ??? a1240xl device 84-pin plastic leaded chip carrier (plcc) ???? ? ?? ?? 100-pin plastic quad flat pack (pqfp) ???? ? ?? ?? 132-pin ceramic pin grid array (cpga) ? ??? ? ? ??? 144-pin plastic quad flat pack (pqfp) ???? ? ?? ?? 176-pin thin plastic quad flat pack (tqfp) ???? ? ?? ?? a1240xlv device 84-pin plastic leaded chip carrier (plcc) ? ? ??? ? ??? 176-pin thin plastic quad flat pack (tqfp) ? ? ??? ? ??? a3265dx device 84-pin plastic leaded chip carrier (plcc) ???? ? ?? ?? 100-pin plastic quad flat pack (pqfp) ???? ? ?? ?? 160-pin plastic quad flat pack (pqfp) ???? ? ?? ?? 176-pin thin plastic quad flat pack (tqfp) ???? ? ?? ?? a3265dxv device 84-pin plastic leaded chip carrier (plcc) ? ? ??? ? ??? 176-pin thin plastic quad flat pack (tqfp) ? ? ??? ? ??? a1280xl device 84-pin plastic leaded chip carrier (plcc) ???? ? ?? ?? 160-pin plastic quad flat pack (pqfp) ???? ? ?? ?? 172-pin ceramic quad flat pack (cqfp) ? ??? ? ? ? ?? 176-pin thin plastic quad flat pack (tqfp) ???? ? ?? ?? 176-pin ceramic pin grid array (cpga) ? ??? ? ? ? ?? 208-pin plastic quad flat pack (pqfp) ???? ? ?? ?? a1280xlv device 84-pin plastic leaded chip carrier (plcc) ? ? ??? ? ??? 176-pin thin plastic quad flat pack (tqfp) ? ? ??? ? ??? a32100dx device 84-pin ceramic quad flat pack (cqfp) ? ??? ? ? ? ?? 84-pin plastic leaded chip carrier (plcc) ????? ?? ?? 160-pin plastic quad flat pack (pqfp) ????? ?? ?? 208-pin plastic quad flat pack (pqfp) ????? ?? ?? contact your actel sales representative for product availability. applications: c = commercial availability: ? = available *speed grade: ?1 = approx. 15% faster than standard i = industrial p = planned ?2 = approx. 25% faster than standard m = military ? = not planned ?3 = approx. 35% faster than standard ?f = approx. 40% slower than standard ? only std, ? 1, ? 2 speed grade ? only std, ? 1 speed grade
integrator series fpgas: 1200xl and 3200dx families 4v3.0 176-pin thin plastic quad flat pack (tqfp) ????? ?? ?? a32100dxv device 84-pin plastic leaded chip carrier (plcc) ? ? ??? ? ??? 176-pin thin plastic quad flat pack (tqfp) ? ? ??? ? ??? a32140dx device 84-pin plastic leaded chip carrier (plcc) ???? ? ?? ?? 160-pin plastic quad flat pack (pqfp) ???? ? ?? ?? 176-pin thin plastic quad flat pack (tqfp) ???? ? ?? ?? 208-pin plastic quad flat pack (pqfp) ???? ? ?? ?? 256-pin ceramic quad flat pack (cqfp) ? ?? ?? ? ? ?? a32140dxv device 84-pin plastic leaded chip carrier (plcc) ? ? ??? ? ??? 176-pin thin plastic quad flat pack (tqfp) ? ? ??? ? ??? a32200dx device 208-pin plastic quad flat pack (pqfp) ????? ?? ?? 208-pin plastic power quad flat pack (rqfp) ????? ?? ?? 240-pin plastic power quad flat pack (rqfp) ????? ?? ?? 208-pin ceramic quad flat pack (cqfp) ? ?? ?? ? ? ?? 256-pin ceramic quad flat pack (cqfp) ? ?? ?? ? ? ?? a32200dxv device 208-pin plastic quad flat pack (pqfp) ? ? ??? ? ??? 240-pin plastic power quad flat pack (rqfp) ? ? ??? ? ??? a32300dx device 208-pin plastic power quad flat pack (rqfp) ????? ?? ?? 240-pin plastic power quad flat pack (rqfp) ????? ?? ?? 256-pin ceramic quad flat pack (cqfp) ? ?? ?? ? ? ?? a32300dxv device 208-pin plastic power quad flat pack (rqfp) ? ? ??? ? ??? 240-pin plastic power quad flat pack (rqfp) ? ? ??? ? ??? product plan (continued) speed grade* application ? fstd ? 1 ? 2 ? 3cimb contact your actel sales representative for product availability. applications: c = commercial availability: ? = available *speed grade: ? 1 = approx. 15% faster than standard i = industrial p = planned ? 2 = approx. 25% faster than standard m=military ? = not planned ? 3 = approx. 35% faster than standard ? f = approx. 40% slower than standard ? only std, ? 1, ? 2 speed grade only std, ? 1 speed grade
v3.0 5 integrator series fpgas: 1200xl and 3200dx families development tool support the devices are fully supported by actel ? s line of fpga development tools, including the actel desktop series and designer advantage tools. the actel desktop series is an integrated design environment for pcs that includes design entry, simulation, synthesis, and place and route tools. designer advantage, actel ? s suite of fpga development point tools for pcs and workstations, includes the actgen macro builder, timing-driven place and route and analysis tools, and device programming software. in addition, the devices contain actionprobe circuitry that provides built-in access to every node in a design, enabling 100 percent real-time observation and analysis of a device's internal logic nodes without design iteration. the probe circuitry is accessed by silicon explorer ii, an easy-to-use integrated verification and logic analysis tool that can sample data at 100 mhz (asynchronous) or 66 mhz (synchronous). silicon explorer ii attaches to a pc ? s standard com port, turning the pc into a fully functional 18-channel logic analyzer. silicon explorer ii allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to only a few seconds. integrator series architectural overview the 1200xl and 3200dx architecture is composed of fine-grained building blocks which produce fast, efficient logic designs. all devices within the integrator series are composed of logic modules, routing resources, clock networks, and i/o modules which are the building blocks to design fast logic designs. in addition, a subset of devices contain embedded dual-port sram and wide-decode modules. the dual-port sram modules are optimized for high-speed datapath functions such as fifos, lifos, and scratchpad memory. the ? integrator series product profile family ? on page 1 lists the specific logic resources contained within each device. plastic device resources user i/os device plcc 84-pin vqfp 100-pin pqfp 100-pin pqfp 144-pin pqfp 160-pin pqfp 208-pin rqfp 240-pin tqfp 176-pin a1225xl 72 83 83 ????? a1240xl 72 ? 83 104 ??? 103 a3265dx 72 ? 83 ? 125 ?? 126 a1280xl 72 ??? 125 140 ? 140 a32100dx 72 ??? 125 152 ? 142 a32140dx 72 ??? 125 176 ? 150 a32200dx ????? 176* 202 ? a32300dx ????? 176 202 ? package definitions (consult your local actel sales representative for product availability.) plcc = plastic leaded chip carrier, pqfp = plastic quad flat pack, tqfp = thin quad flat pack, bga = ball grid array, vqfp = ve ry thin quad flat pack, rqfp = plastic power quad flat pack * also available in rqfp 208-pin. hermetic device resources user i/os device cpga 176-pin cqfp 84-pin cqfp 172-pin cqfp 208-pin cqfp 256-pin a1280xl 140 ? 140 ?? a32100dx ? 60 ??? a32140dx ???? 176 a32200dx ??? 176 202 a32300dx ???? 212 package definitions (consult your local actel sales representative for product availability.) cpga = ceramic pin grid array, cqfp = ceramic quad flat pack
integrator series fpgas: 1200xl and 3200dx families 6v3.0 logic modules 3200dx and 1200xl devices contain three types of logic modules: combinatorial (c-modules), sequential (s-modules), and decode (d-modules). 1200xl devices contain only the c-module and s-module, while the 3200dx devices contain d-modules and dual-port sram modules in addition to the s-module and c-module. the c-module is shown in figure 1 and implements the following function: y=!s1*!s0*d00+!s1*s0*d01+s1*!s0*d10+s1*s0*d11 where: s0=a0*b0 s1=a1+b1 the s-module shown in figure 2 is designed to implement high-speed sequential functions within a single logic module. the s-module implements the same combinatorial logic function as the c-module while adding a sequential element. the sequential element can be configured as either a d-type flip-flop or a transparent latch. to increase flexibility, the s-module register can be bypassed so that it implements purely combinatorial logic. figure 1 ? c-module implementation d00 d01 d10 d11 s0 s1 y a0 b0 a1 b1 figure 2 s-module implementation d11 d01 d00 d10 y out s1 s0 up to 7-input function plus d-type flip-flop with clear d11 d01 d00 d10 y s1 s0 up to 7-input function plus latch y up to 4-input function plus latch with clear d11 d01 d00 d10 yout s1 s0 up to 8-input function (same as c-module) s d1 d0 clr dq out clr dq out gate dq gate
v3.0 7 integrator series fpgas: 1200xl and 3200dx families 3200dx devices contain a third type of logic module, d-modules, which are arranged around the periphery of the device. d-modules contain wide-decode circuitry which provides a fast, wide-input and function similar to that found in product term architectures ( figure 3 ). the d-module allows 3200dx devices to perform wide-decode functions at speeds comparable cplds and pal devices. the output of the d-module has a programmable inverter for active high or low assertion. the d-module output is hard-wired to an output pin or can be fed back into the array to be incorporated into other logic. dual-port sram modules several 3200dx devices contain dual-port sram modules that have been optimized for synchronous or asynchronous applications. the sram modules are arranged in 256-bit blocks which can be configured as 32x8 or 64x4 (refer to ? integrator series product profile family ? on page 1 for the number of sram blocks within a particular device). sram modules can be cascaded together to form memory spaces of user-definable width and depth. a block diagram of the 3200dx dual-port sram block is shown in figure 4 . the 3200dx sram modules are true dual-port structures containing independent read and write ports. each sram module contains six bits of read and write addressing (rdad[5:0] and wrad[5:0], respectively) for 64x4 bit blocks. when configured in byte mode, the highest order address bits (rdad5 and wrad5) are not used. the read and write ports of the sram block contain independent clocks (rclk and wclk) with programmable polarities offering active high or low implementation. the sram block contains eight data inputs (wd[7:0]) and eight outputs (rd[7:0]) which are connected to segmented vertical routing tracks. the 3200dx dual-port sram blocks provide an optimal solution for high-speed buffered applications requiring fast fifo and lifo queues. actel ? s actgen macro builder provides the capability to quickly design memory functions, figure 3 d-module implementation 7 inputs hard-wire to i/o feedback to array programmable inverter figure 4 3200dx dual-port sram block sram module 32 x 8 or 64 x 4 (256 bits) read port logic write port logic rd[7:0] routing tracks latches read logic [5:0] rdad[5:0] ren rclk latches wd[7:0] latches wrad[5:0] write logic mode blken wen wclk [5:0] [7:0]
integrator series fpgas: 1200xl and 3200dx families 8v3.0 such as fifos, lifos, and ram arrays. additionally, unused sram blocks can be used to implement registers for other logic within the design. i/o modules the i/o modules provide the interface between the device pins and the logic array. figure 5 is a block diagram of the i/o module. a variety of user functions, determined by a library macro selection, can be implemented in the module (refer to the macro library guide for more information). i/o modules contain a tri-state buffer, input and output latches which can be configured for input, output, or bi-directional pins ( figure 5 ). the integrator series devices contain flexible i/o structures where each output pin has a dedicated output enable control. the i/o module can be used to latch input and/or output data, providing a fast set-up time. in addition, the actel designer series software tools can build a d-type flip-flop using a c-module to register input and/or output signals. actel ? s designer series development tools provide a design library of i/o macrofunctions which can implement all i/o configurations supported by the integrator series fpgas. routing structure the integrator series architecture uses vertical and horizontal routing tracks to interconnect the various logic and i/o modules. these routing tracks are metal interconnects that may either be of continuous length or broken into pieces called segments. varying segment lengths allows interconnection of over 90% of design tracks to occur with only two antifuse connections. segments can be joined together at the ends using antifuses to increase their lengths up to the full length of the track. all interconnects can be accomplished with a maximum of four antifuses. horizontal routing horizontal channels are located between the rows of modules and are composed of several routing tracks. the horizontal routing tracks within the channel are divided into one or more segments. the minimum horizontal segment length is the width of a module pair, and the maximum horizontal segment length is the full length of the channel. any segment that spans more than one-third the row length is considered a long horizontal segment. a typical channel is shown in figure 6 . non-dedicated horizontal routing tracks are used to route signal nets; dedicated routing tracks are used for the global clock networks and for power and ground tie-off tracks. vertical routing another set of routing tracks run vertically through the module. vertical tracks are of three types: input, output, and long, and are divided into one or more segments. each segment in an input track is dedicated to the input of a particular module; each segment in an output track is dedicated to the output of a particular module. long segments are uncommitted and can be assigned during routing. each output segment spans four channels (two above and two below), except near the top and bottom of the array where edge effects occur. long vertical tracks contain either one or two segments. an example of vertical routing tracks and segments is shown in figure 6 . antifuse structure an antifuse is a ? normally open ? structure as opposed to the normally closed fuse structure used in proms or pals. the use of antifuses to implement a programmable logic device results in highly-testable structures as well as efficient figure 5 i/o module g/clk* qd en pad * can be configured as a latch or d flip-flop from array to a rr a y (using c-module) g/clk* qd figure 6 routing structure vertical routing tracks antifuses logic segmented horizontal routing tracks modules
v3.0 9 integrator series fpgas: 1200xl and 3200dx families programming algorithms. the structure is highly testable because there are no pre-existing connections; therefore, temporary connections can be made using pass transistors. these temporary connections can isolate individual antifuses to be programmed and individual circuit structures to be tested, which can be done before and after programming. for example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. clock networks two low-skew, high-fanout clock distribution networks are provided in each 3200dx device. these networks are referred to as clk0 and clk1. each network has a clock module (clkmod) that selects the source of the clock signal and may be driven as follows: 1. externally from the clka pad 2. externally from the clkb pad 3. internally from the clkina input 4. internally from the clkinb input the clock modules are located in the top row of i/o modules. clock drivers and a dedicated horizontal clock track are located in each horizontal routing channel. the user controls the clock module by selecting one of two clock macros from the macro library. the macro clkbuf is used to connect one of the two external clock pins to a clock network, and the macro clkint is used to connect an internally-generated clock signal to a clock network. since both clock networks are identical, the user does not care whether clk0 or clk1 is being used. the clock input pads may also be used as normal i/os, bypassing the clock networks (see figure 7 ). the 3200dx devices which contain sram modules (all except a3265dx and a32140dx) have four additional register control resources, called quadrant clock networks ( figure 8 on page 10 ). each quadrant clock provides a local, high-fanout resource to the contiguous logic modules within its quadrant of the device. quadrant clock signals can originate from specific i/o pins or from the internal array and can be used as a secondary register clock, register clear, or output enable. test circuitry all devices contain actel ? s actionprobe test circuitry which test and debug a design once it is programmed into a device. once a device has been programmed, the actionprobe test circuitry allows the designer to probe any internal node during device operation to aid in debugging a design. in addition, 3200dx devices contain ieee standard 1149.1 boundary scan test circuitry. ieee standard 1149.1 boundary scan testing (bst) ieee standard 1149.1 defines a four-pin test access port (tap) interface for testing integrated circuits in a system. the 3200dx family provides five bst pins: test data in (tdi), test data out (tdo), test clock (tck), and test mode select test reset (trst) (3200dx24a only). devices are configured in a test ? chain ? where bst data can be transmitted serially between devices via tdo-to-tdi interconnections. the tms and tck signals are shared among all devices in the test chain so that all components operate in the same state. the 3200dx family implements a subset of the ieee standard 1149.1 bst instruction in addition to a private instruction, which allows the use of actel ? s actionprobe facility with bst. refer to the ieee standard 1149.1 specification for detailed information regarding bst. boundary scan circuitry the 3200dx boundary scan circuitry consists of a test access port (tap) controller, test instruction register, a jprobe register, a bypass register, and a boundary scan register. figure 9 on page 10 shows a block diagram of the 3200dx boundary scan circuitry. when a device is operating in bst mode, four i/o pins are used for the tdi, tdo, tms, and tck signals. an active reset (ntrst) pin is not supported; however, the 3200dx device contain power-on circuitry that resets the boundary scan circuitry upon power-up. table 1 on page 11 summarizes the functions of the ieee 1149.1 bst signals. figure 7 clock networks clkb clka from pads clock drivers clkmod clkinb clkina s0 s1 internal signal clko(17) clko(16) clko(15) clko(2) clko(1) clock tracks
integrator series fpgas: 1200xl and 3200dx families 10 v3.0 figure 8 quadrant clock network figure 9 3200dx ieee 1149.1 boundary scan circuitry quad clock module qclka qclkb *qclk1in s0 s1 qclk1 quad clock module *qclk2in s0 s1 qclk2 quad clock module qclkc qclkd *qclk3in s0 s1 qclk3 quad clock module *qclk4in s0 s1 qclk4 *qclk1in, qclk2in, qclk3in, and qclk4in are internally-generated signals. jprobe register boundary scan register instruction decode control logic tap controller instruction register bypass register tms tck tdi output mux tdo jtag jtag
v3.0 11 integrator series fpgas: 1200xl and 3200dx families jtag all 3200dx devices are ieee 1149.1 (jtag) compliant. 3200dx devices offer superior diagnostic and testing capabilities by providing jtag and probing capabilites. these functions are controlled through the special jtag pins in conjunction with the program fuse. jtag fuse programmed: tck must be terminated ? logical high or low doesn ? t matter (to avoid floating input) tdi, tms may float or at logical high (internal pull-up is present) tdo may float or connect to tdi of another device (it ? s an output) jtag fuse not programmed: tck, tdi, tdo, tms are user i/o. if not used, they will be configured as tristated output. bst instructions boundary scan testing within the 3200dx devices is controlled by a test access port (tap) state machine. the tap controller drives the three-bit instruction register, a bypass register, and the boundary scan data registers within the device. the tap controller uses the tms signal to control the testing of the device. the bst mode is determined by the bitstream entered on the tms pin. table 2 describes the test instructions supported by the 3200dx devices. reset the tms pin is equipped with an internal pull-up resistor. this allows the tap controller to remain in or return to the test-logic-reset state when there is no input or when a logical 1 is on the tms pin. to reset the controller, tms must be high for at least five tck cycles. when a device is operating in bst mode, four i/o pins are used for the tdi, tdo, tms, and tclk signals. an active reset (ntrst) pin is not supported; however, the 3200dx contains power-on circuitry which automatically resets the bst circuitry upon power-up. the following table summarizes the functions of the bst signals. jtag bst instructions jtag bst testing within the 3200dx devices is controlled by a test access port (tap) state machine. the tap controller drives the three-bit instruction register, a bypass register, and the boundary scan data registers within the device. the tap controller uses the tms signal to control the jtag testing of the device. the jtag test mode is determined by the bitstream entered on the tms pin. the table in the next column describes the jtag instructions supported by the 3200dx. design tool support actionprobe if a device has been successfully programmed and the security fuse has not been programmed, any internal logic or i/o module output can be observed in real time using the actionprobe circuitry, the pra and/or prb pins, and actel ? s silicon explorer diagnostic and debug tool kit. table 1 ieee 1149.1 bst signals signal name function tdi test data in serial data input for bst instructions and data. data is shifted in on the rising edge of tck. tdo test data out serial data output for bst instructions and test data. tms test mode select serial data input for bst mode. data is shifted in on the rising edge of tck. tck test clock clock signal to shift the bst data into the device. table 2 bst instructions test mode code description extest 000 allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. sample/ preload 001 allows a snapshot of the signals at the device pins to be captured and examined during device operation. jprobe 011 a private instruction allowing the user to connect actel ? s micro probe registers to the test chain. user instruction 100 allows the user to build application-specific instructions such as ram read and ram write. high z 101 refer to the ieee standard 1149.1 specification. clamp 110 refer to the ieee standard 1149.1 specification. bypass 111 enables the bypass register between the tdi and tdo pins. the test data passes through the selected device to adjacent devices in the test chain.
integrator series fpgas: 1200xl and 3200dx families 12 v3.0 5.0v operating conditions absolute maximum ratings 1 free air temperature range symbol parameter limits units v cc dc supply voltage ? 0.5 to +7.0 v v i 2 input voltage ? 0.5 to v cc +0.5 v v o output voltage ? 0.5 to v cc +0.5 v t stg storage temperature ? 65 to +150 c notes: 1. stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. device should not be operated outside the recommended operating conditions. 2. device inputs are normally high impedance and draw extremely low current. however, when input voltage is greater than v cc + 0.5v or less than gnd ? 0.5v, the internal protection diode will be forward biased and can draw excessive current. recommended operating conditions parameter commercial industrial military units temperature range 1 0 to +70 ? 40 to +85 ? 55 to +125 c power supply tole ran ce 5 10 10 % v cc note: 1. ambient temperature (t a ) is used for commercial and industrial; case temperature (t c ) is used for military. electrical specifications symbol parameter commercial commercial ? f industrial military units min. max. min. max. min. max. min. max. v oh 1 (i oh = ? 10 ma) 2.4 2.4 v (i oh = ? 6 ma) 3.84 3.84 v (i oh = ? 4 ma) 3.7 3.7 v v ol 1 (i ol = 10 ma) 0.5 0.5 v (i ol = 6 ma) 0.33 0.33 0.40 0.40 v v il ? 0.3 0.8 ? 0.3 0.8 ? 0.3 0.8 ? 0.3 0.8 v v ih 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 v input transition time t r , t f 500 500 500 500 ns c io i/o capacitance 2 10 10 10 10 pf standby current, i cc 3 (typical = 1 ma) 2.0 20 10 20 ma i cc(d) dynamic v cc supply current see the ? power dissipation ? section on page 14. iv curve 4 can be converted from ibis model on the web. notes: 1. only one output tested at a time. v cc = min. 2. includes worst-case 176 cpga package capacitance. v out = 0 v, f = 1 mhz. 3. all outputs unloaded. all inputs = v cc or gnd, typical i cc = 1 ma. i cc limit includes i pp and i sv during normal operation. 4. the ibis model can be found at www.actel.com/support/support/support_ibis.html.
v3.0 13 integrator series fpgas: 1200xl and 3200dx families 3.3v operating conditions absolute maximum ratings 1 free air temperature range recommended operating conditions symbol parameter limits units v cc dc supply voltage ? 0.5 to +7.0 v v i 2 input voltage ? 0.5 to v cc +0.5 v v o output voltage ? 0.5 to v cc +0.5 v t stg storage temperature ? 65 to +150 c notes: 1. stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. device should not be operated outside the recommended operating conditions. 2. device inputs are normally high impedance and draw extremely low current. however, when input voltage is greater than v cc + 0.5v or less than gnd ? 0.5v, the internal protection diodes will forward bias and can draw excessive current. parameter commercial units temperature range 1 0 to +70 c power supply tolerance 5 %v note: 1. ambient temperature (t a ) is used for commercial. electrical specifications parameter commercial units min. max. v oh 1 (i oh = ? 4 ma) 2.15 v (i oh = ? 3.2 ma) 2.4 v v ol 1 (i ol = 6 ma) 0.4 v v il ? 0.3 0.8 v v ih 2.0 v cc + 0.3 v input transition time t r , t f 2 500 ns c io i/o capacitance 2, 3 10 pf standby current, i cc 4 (typical = 0.3 ma) 0.75 ma i cc(d) dynamic v cc supply current see the ? power dissipation ? section on page 14. iv curve 4 can be converted from ibis model on the web. notes: 1. only one output tested at a time. v cc = min. 2. includes worst-case 84-pin plcc package capacitance. v out = 0 v, f = 1 mhz. 3. typical standby current = 0.3 ma. all outputs unloaded. all inputs = v cc or gnd. 4. the ibis model can be found at www.actel.com/support/support/support_ibis.html.
integrator series fpgas: 1200xl and 3200dx families 14 v3.0 package thermal characteristics the device junction to case thermal characteristic is jc , and the junction to ambient air characteristic is ja . the thermal characteristics for ja are shown with two different air flow rates. maximum junction temperature is 150 c. a sample calculation of the absolute maximum power dissipation allowed for a pqfp 160-pin package with still air at commercial temperature is as follows: power dissipation general power equation p = [i cc standby + i cc active] * v cc + i ol * v ol * n + i oh * (v cc ? v oh ) * m where: i cc standby is the current flowing when no inputs or outputs are changing. i cc active is the current flowing due to cmos switching. i ol , i oh are ttl sink/source currents. v ol , v oh are ttl level output voltages. n equals the number of outputs driving ttl loads to v ol . m equals the number of outputs driving ttl loads to v oh . an accurate determination of n and m is problematic because their values depend on the family type, design details, and on the system i/o. the power can be divided into two components: static and active. static power component actel fpgas have small static power components that result in lower power dissipation than pals or plds. by integrating multiple pals/plds into one fpga, an even greater reduction in board-level power dissipation can be achieved. the power dissipation due to standby current is typically a small component of the overall power. standby power is calculated below for commercial worst case conditions. i cc v cc power 2 ma 5.25 v 10.5 mw the static power dissipation by ttl loads depends on the number of outputs driving high or low and the dc load current. again, this number is typically small. for instance, a 32-bit bus sinking 4 ma at 0.33v will generate 42 mw with all outputs driving low and 140 mw with all outputs driving high. the actual dissipation will average somewhere in between as i/os switch states with time. active power component power dissipation in cmos devices is usually dominated by the active (dynamic) power dissipation. this component is frequency-dependent, a function of the logic and the external i/o. active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to pc board traces and load device inputs. an additional component of the active power dissipation is the totem pole current in the cmos transistor pairs. the net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. package type pin count ja maximum power dissipation still air 300 ft/min still air 300 ft/min plastic quad flat pack 100 42 c/w 33 c/w 1.9 w 2.4 w plastic quad flat pack 144 36 c/w 29 c/w 2.2 w 2.8 w plastic quad flat pack 160 34 c/w 27 c/w 2.4 w 3.0 w plastic quad flat pack 208 25 c/w 16.2 c/w 3.2 w 4.9 w plastic leaded chip carrier 84 37 c/w 28 c/w 2.2 w 2.9 w thin quad flat pack 176 32 c/w 25 c/w 2.5 w 3.2 w power quad flat pack 208 16.8 c/w 11.4 c/w 4.8 w 7.0 w power quad flat pack 240 16.1 c/w 10.6 c/w 5.0 w 7.5 w very thin quad flat pack 100 43 c/w 35 c/w 1.9 w 2.3 w max. junction temp. (c) ? max. commercial temp. ja (c/w) ----------------------------------------------------------------------------------------------------------------------------- 150c ? 70c 34c/w --------------------------------- 2.4 w ==
v3.0 15 integrator series fpgas: 1200xl and 3200dx families equivalent capacitance the power dissipated by a cmos circuit can be expressed by equation 1 power (w) = c eq * v cc 2 * f (1) where: c eq is the equivalent capacitance expressed in picofarads (pf). v cc is power supply in volts (v). f is the switching frequency in megahertz (mhz). equivalent capacitance is calculated by measuring i ccactive at a specified frequency and voltage for each circuit component of interest. measurements have been made over a range of frequencies at a fixed value of v cc . equivalent capacitance is frequency-independent, so the results may be used over a wide range of operating conditions. equivalent capacitance values are shown below. c eq values for actel fpgas modules (c eqm )5.2 input buffers (c eqi ) 11.6 output buffers (c eqo ) 23.8 routed array clock buffer loads (c eqcr )3.5 to calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. equation 2 shows a piece-wise linear summation over all components. power = v cc 2 * [(m x c eqm * f m ) modules + (n * c eqi * f n ) inputs + (p * ( c eqo + c l ) * f p ) outputs + 0.5 * (q 1 * c eqcr * f q1 ) routed_clk1 + (r 1 * f q1 ) routed_clk1 + 0.5 * (q 2 * c eqcr * f q2 ) routed_clk2 + (r 2 * f q2 ) routed_clk2 (2) where: fixed capacitance values for actel fpgas (pf) determining average switching frequency to determine the switching frequency for a design, the user must have a detailed understanding of the data input values to the circuit. the following guidelines represent worst-case scenarios; they can be generally used to predict the upper limits of power dissipation. m = number of logic modules switching at frequency f m n = number of input buffers switching at frequency f n p = number of output buffers switching at frequency f p q 1 = number of clock loads on the first routed array clock q 2 = number of clock loads on the second routed array clock r 1 = lfixed capacitance due to first routed array clock r 2 = fixed capacitance due to second routed array clock c eqm = equivalent capacitance of logic modules in pf c eqi = equivalent capacitance of input buffers in pf c eqo = equivalent capacitance of output buffers in pf c eqcr = equivalent capacitance of routed array clock in pf c l = output load capacitance in p f m = average logic module switching rate in mhz f n = average input buffer switching rate in mhz f p = average output buffer switching rate in mhz f q1 = average first routed array clock rate in mhz f q2 = average second routed array clock rate in mhz table 5. device type r 1 routed_clk1 r 2 routed_clk2 a1225xl 106 106 a1240xl 134 134 a3265dx 158 158 a1280xl 168 168 a32100dx 178 178 a32140dx 190 190 a32200dx 230 230 a32300dx 285 285 logic modules (m) = 80% of combinatorial modules inputs switching (n) = # of inputs/4 outputs switching (p) = # outputs/4 first routed array clock loads (q 1 ) = 40% of sequential modules second routed array clock loads (q 2 ) = 40% of sequential modules load capacitance (c l ) = 35 pf average logic module switching rate (f m ) =f/10 average input switching rate (f n ) =f/5 average output switching rate (f p ) =f/10 average first routed array clock rate (f q1 ) =f average second routed array clock rate (f q2 ) =f/2
integrator series fpgas: 1200xl and 3200dx families 16 v3.0 1200xl timing model* notes: 1. *values shown for a1225xl-2 at worst-case commercial conditions. ? 2. input module predicted routing delay output delays internal delays input delays t inh = 0.0 ns t insu = 0.3 ns i/o module d q t ingl = 2.6 ns t inyl = 1.3 ns t ird2 = 3.2 ns ? combinatorial logic module t pd = 2.6 ns sequential logic module i/o module t rd1 = 0.8 ns t dlh = 3.8 ns i/o module array clocks f max = 225 mhz combin- atorial logic included in t sud d q d q t outh = 0.0 ns t outsu = 0.3 ns t glh = 4.2 ns t dlh = 3.8 ns t enhz = 5.4 ns t rd1 = 0.8 ns t co = 2.6 ns t sud = 0.4 ns t hd = 0.0 ns t rd4 = 2.0 ns t rd8 = 3.2 ns predicted routing delays t ckh = 5.7 ns g g fo = 256 t rd2 = 1.3 ns t lco = 10.7 ns (64 loads, pad-pad)
v3.0 17 integrator series fpgas: 1200xl and 3200dx families 3200dx timing model (logic functions using array clocks)* *values shown for a3265dx-2 at worst-case commercial conditions. output delays internal delays input delays t inh = 0.0 ns t insu = 0.4 ns i/o module d q t ingo = 2.8 ns t inpy = 1.2 ns t ird1 = 2.7 ns combinatorial module t pd = 2.1 ns sequential logic module i/o module t rd1 = 0.3 ns t dlh = 3.2 ns i/o module array clocks f max = 173 mhz combin- atorial logic included in t sud d q d q t lh = 0.0 ns t lsu = 0.4 ns t ghl = 6.5 ns t dlh = 3.2 ns t enhz = 7.1 ns t rd1 = 0.3 ns t co = 2.0 ns t sud = 0.3 ns t hd = 0.0 ns predicted routing delays g g decode module t pdd = 2.1 ns t rdd = 0.4 ns t rd2 = 0.7 ns t rd4 = 1.2 ns t ckh = 5.3 ns
integrator series fpgas: 1200xl and 3200dx families 18 v3.0 3200dx timing model (logic functions using quadrant clocks)* * preliminary values shown for a32200dx-3 at worst-case commercial conditions. ** load-dependent. output delays internal delays input delays t inh = 0.0 ns t insu = 0.45 ns i/o module d q t ingo = 3.3 ns t inpy = 1.4 ns t ird1 = 1.9 ns combinatorial module t pd = 2.0 ns sequential logic module i/o module t rd1 = 1.1 ns t dlh = 3.7 ns i/o module quadrant clocks f max = 165 mhz combin- atorial logic included in t sud d q d q t lh = 0.0 ns t lsu = 0.26 ns t ghl = 8.9 ns t dlh = 3.7 ns t enhz = 8.3 ns t rd1 = 1.1 ns t co = 2.3 ns t sud = 0.3 ns t hd = 0.0 ns predicted routing delays g g decode module t pdd = 2.5 ns t rdd = 0.3 ns t rd2 = 1.7 ns t rd4 = 2.6 ns t ckh = 5.3 ns**
v3.0 19 integrator series fpgas: 1200xl and 3200dx families 3200dx timing model (sram functions)* *values shown for a32200dx-3 at worst-case commercial conditions. t inh = 0.05 ns t insu = 0.45 ns input delays i/o module d q t ingo = 3.3 ns t inpy = 1.4 ns t ird1 = 1.9 ns array clocks f max = 165 mhz g t ghl = 8.9 ns t lsu = 0.26 ns i/o module d q t lh = 0.0 ns t dlh = 3.7 ns g wd [7:0] wrad [5:0] blken wen wclk t adsu = 1.5 ns t adh = 0.0 ns t wensu = 2.6 ns t bens = 2.6 ns rd [7:0] rdad [5:0] ren rclk t adsu = 1.5 ns t adh = 0.0 ns t rensua = 0.6 ns t rd1 = 1.1 ns predicted routing delays t rco = 3.2 ns
integrator series fpgas: 1200xl and 3200dx families 20 v3.0 parameter measurement output buffer delays ac test loads input buffer delays module delays to ac test loads (shown below) pad d e tribuff in 50% pa d v ol v oh 1.5v t dlh 50% 1.5v t dhl e 50% pa d v ol 1.5v t enzl 50% 10% t enlz e 50% pad gnd v oh 1.5v t enzh 50% 90% t enhz v cc load 1 (used to measure propagation delay) load 2 (used to measure rising/falling edges) 35 pf to the output under test v cc gnd 35 pf to the output under test r to v cc for t plz /t pzl r to gnd for t phz /t pzh r = 1 k ? pad y inbuf pad 3v 0v 1.5v y gnd v cc 50% t inyh 1.5v 50% t inyl s a b y s, a or b y 50% t plh y 50% 50% 50% 50% 50% t phl t phl t plh
v3.0 21 integrator series fpgas: 1200xl and 3200dx families sequential module timing characteristics flip-flops and latches note: d represents all data functions involving a, b, and s for multiplexed flip-flops. (positive edge triggered) d e clk clr pre y d 1 g, c l k e q pre, clr t wclka t wasyn t hd t suena t sud t rs t a t wclki t co t hena
integrator series fpgas: 1200xl and 3200dx families 22 v3.0 sequential timing characteristics (continued) output buffer latches input buffer latches g pad pad clk data g clk t inh clkbuf t insu t suext t hext ibdl data d g t outsu t outh pad obdlhs d g
v3.0 23 integrator series fpgas: 1200xl and 3200dx families decode module timing sram timing characteristics a ? g, h y t plh 50% v cc v cc t phl y a b c d e f g h wrad [5:0] blken wen wclk rdad [5:0] lew ren rclk rd [7:0] wd [7:0] write port read port ram array 32x8 or 64x4 (256 bits)
integrator series fpgas: 1200xl and 3200dx families 24 v3.0 dual-port sram timing waveforms 3200dx sram synchronous read operation 3200dx sram write operation note: identical timing for falling-edge clock. note: identical timing for falling-edge clock. wclk wd[7:0] wrad[5:0] wen blken valid valid t rckhl t rckhl t wensu t bensu t wenh t benh t adsu t adh rclk ren rdad[5:0] rd[7:0] old data valid t rckhl t ckhl t renh t rco t adh t doh t adsu new data t rensu
v3.0 25 integrator series fpgas: 1200xl and 3200dx families 3200dx sram asynchronous read operation?type 1 3200dx sram asynchronous read operation?type 2 (read address controlled) (write address controlled) rdad[5:0] rd[7:0] data 1 t rdadv t doh addr2 addr1 data 2 t rpd wen wd[7:0] wclk rd[7:0] old data valid t wenh t rpd t wensu new data t doh t adsu wrad[5:0] blken t adh
integrator series fpgas: 1200xl and 3200dx families 26 v3.0 predictable performance: tight delay distributions propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. propagation delay increases as the length of routing tracks, the number of interconnect elements, or the number of inputs increase. from a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. higher fanout usually requires some paths to have longer routing tracks. the integrator series delivers a very tight fanout delay distribution. this tight distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. actel ? s patented plice antifuse offers a very low resistive/capacitive interconnect. the antifuses, fabricated in 0.6 micron lithography, offer nominal levels of 100 ohms resistance and 7.0 femtofarad (ff) capacitance per antifuse. the integrator series fanout distribution is also tight due to the low number of antifuses required for each interconnect path. the proprietary architecture limits the number of antifuses per path to a maximum of four, with 90% of interconnects using two antifuses. timing characteristics timing characteristics for devices fall into three categories: family-dependent, device-dependent, and design-dependent. the input and output buffer characteristics are common to all integrator series members. internal routing delays are device-dependent. design dependency means actual delays are not determined until after placement and routing of the user ? s design is complete. delay values may then be determined by using the designer series utility or performing simulation with post-layout delays. critical nets and typical nets propagation delays in this data sheet apply to typical nets, which are used for initial design performance evaluation. the abundant routing resources in the integrator series architecture allows for deterministic timing. using directtime, a timing-driven place and route tool in actel ? s designer series development software, the designer may specify timing-critical nets and system clock frequency. using these timing specifications, the place and route software optimize the design layout to meet the user ? s specifications. long tracks some nets in the design use long tracks, which are special routing resources that span multiple rows, columns, or modules. long tracks employ three and sometimes four antifuse connections. this increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. typically, up to 6% of nets in a fully utilized device require long tracks. long tracks contribute approximately 3 ns to 6 ns delay, which is represented statistically in higher fanout (fo=8) routing delays in the data sheet specifications section. timing derating a timing derating factor of 0.45 is used to reflect best-case processing. note that this factor is relative to the ? standard speed ? timing parameters, and must be multiplied by the appropriate voltage and temperature derating factors for a given application. timing derating factor (temperature and voltage) timing derating factor for designs at typical temperature (t j = 25 c) and voltage (5.0v) note: this derating factor applies to all routing and propagation delays. industrial military min. max. min. max. (commercial specification) x 0.69 1.11 0.67 1.23 (maximum specification, worst-case condition) x 0.85
v3.0 27 integrator series fpgas: 1200xl and 3200dx families temperature and voltage derating factors (normalized to worst-case commercial, t j = 4.75v, 70 c) ? 55 ? 400 257085125 4.50 0.75 0.79 0.86 0.92 1.06 1.11 1.23 4.75 0.71 0.75 0.82 0.87 1.00 1.05 1.16 5.00 0.69 0.72 0.80 0.85 0.97 1.02 1.13 5.25 0.68 0.69 0.77 0.82 0.95 0.98 1.09 5.50 0.67 0.69 0.76 0.81 0.93 0.97 1.08 note: this derating factor applies to all routing and propagation delays. 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 4.50 4.75 5.00 5.25 5.50 derating factor 125?c 85?c 70?c 25?c 0?c ?0?c ?5?c junction temperature and voltage derating curves (normalized to worst-case commercial, t j = 4.75v, 70 c)
integrator series fpgas: 1200xl and 3200dx families 28 v3.0 a1225xl timing characteristics (worst-case commercial conditions, v cc = 4.75 v, t j = 70 c) notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtai ned from the directtime analyzer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se t-up/hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal set-up (hold) time. 5. v cc = 3.0v for 3.3v specifications. ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units logic modulepropagation delays 1 t pd1 single module 2.6 3.0 3.5 5.0 4.2 ns t co sequential clk-to-q 2.6 3.0 3.5 5.0 4.2 ns t go latch g-to-q 2.6 3.0 3.5 5.0 4.2 ns t rs flip-flop (latch) reset-to-q 2.6 3.0 3.5 5.0 4.2 ns predicted routing delays 2 t rd1 fo=1 routing delay 0.8 0.9 1.1 1.57 1.3 ns t rd2 fo=2 routing delay 1.3 1.4 1.7 2.43 2.0 ns t rd3 fo=3 routing delay 1.7 1.8 2.2 3.15 2.6 ns t rd4 fo=4 routing delay 2.0 2.3 2.7 3.86 3.2 ns t rd8 fo=8 routing delay 3.2 3.5 4.2 6.00 5.0 ns sequential timing characteristics 3,4 t sud flip-flop (latch) data input set-up 0.4 0.4 0.5 0.7 0.6 ns t hd flip-flop (latch) data input hold 0.0 0.0 0.0 0.0 0.0 ns t suena flip-flop (latch) enable set-up 0.8 0.9 1.0 1.4 1.2 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 3.2 3.6 4.3 6.1 5.2 ns t wasyn flip-flop (latch) asynchronous pulse width 3.2 3.6 4.3 6.1 5.2 ns t a flip-flop clock input period 6.5 7.4 8.7 12.4 10.4 ns t inh input buffer latch hold 0.0 0.0 0.0 0.0 0.0 ns t insu input buffer latch set-up 0.3 0.4 0.4 0.6 0.5 ns t outh output buffer latch hold 0.0 0.0 0.0 0.0 0.0 ns t outsu output buffer latch set-up 0.3 0.4 0.4 0.6 0.5 ns f max flip-flop (latch) clock frequency 225 200 170 120 115 mhz
v3.0 29 integrator series fpgas: 1200xl and 3200dx families a1225xl timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance. ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. units input module propagation delays t inyh pad-to-y high 1.1 1.2 1.4 2.0 1.7 ns t inyl pad-to-y low 1.3 1.4 1.7 2.4 2.0 ns t ingh g-to-y high 2.0 2.3 2.7 3.9 3.2 ns t ingl g-to-y low 2.6 3.0 3.5 5.0 4.2 ns input module predicted routing delays 1 t ird1 fo=1 routing delay 2.9 3.3 3.9 5.6 4.7 ns t ird2 fo=2 routing delay 3.2 3.6 4.3 6.1 5.2 ns t ird3 fo=3 routing delay 3.8 4.2 5.0 7.2 6.0 ns t ird4 fo=4 routing delay 4.1 4.6 5.4 7.7 6.5 ns t ird8 fo=8 routing delay 5.2 5.9 6.9 9.9 8.3 ns global clock network t ckh input low to high fo = 32 fo = 256 5.1 5.7 5.8 6.5 6.8 7.6 9.7 10.9 8.2 9.1 ns t ckl input high to low fo = 32 fo = 256 5.0 5.7 5.7 6.5 6.7 7.6 9.6 10.9 8.0 9.1 ns t pwh minimum pulse width high fo = 32 fo = 256 2.6 2.7 3.0 3.1 3.5 3.6 5.0 5.1 4.2 4.3 ns t pwl minimum pulse width low fo = 32 fo = 256 2.6 2.7 3.0 3.1 3.5 3.6 5.0 5.1 4.2 4.3 ns t cksw maximum skew fo = 32 fo = 256 0.8 0.8 0.9 0.9 1.0 1.0 1.4 1.4 1.2 1.2 ns t suext input latch external set-up fo = 32 fo = 256 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns t hext input latch external hold fo = 32 fo = 256 2.6 3.2 2.9 3.7 3.4 4.3 4.9 6.1 4.1 5.2 ns t p minimum period fo = 32 fo = 256 5.4 5.6 6.1 6.3 7.2 7.4 10.3 10.6 8.6 8.9 ns f max maximum frequency fo = 32 fo = 256 225 200 200 180 170 155 120. 105 115 105 mhz
integrator series fpgas: 1200xl and 3200dx families 30 v3.0 a1225xl timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) note: 1. delays based on 35 pf loading. ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min.max.min.max.min.max.min.max.min.max.units ttl output module timing 1 t dlh data-to-pad high 3.8 4.3 5.0 7.1 6.0 ns t dhl data-to-pad low 4.1 4.6 5.4 7.7 6.5 ns t enzh enable-pad z to high 3.8 4.3 5.0 7.1 6.0 ns t enzl enable-pad z to low 4.1 4.7 5.5 7.9 6.5 ns t enhz enable-pad high to z 5.4 6.1 7.2 10.3 8.6 ns t enlz enable-pad low to z 5.4 6.1 7.2 10.3 8.6 ns t glh g-to-pad high 4.2 4.8 5.6 8.0 6.7 ns t ghl g-to-pad low 4.7 5.4 6.3 9.0 7.6 ns t lco i/o latch clock-out (pad-to-pad), 64 clock loading 9.0 10.0 12.0 17.2 14.4 ns t aco array clock-out (pad-to-pad), 64 clock loading 12.8 14.4 17.0 24.3 20.4 ns d tlh capacitive loading, low to high 0.04 0.04 0.05 0.06 0.06 ns/pf d thl capacitive loading, high to low 0.05 0.06 0.07 0.08 0.08 ns/pf cmos output module timing 1 t dlh data-to-pad high 4.8 5.4 6.4 9.1 7.7 ns t dhl data-to-pad low 3.4 3.8 4.5 6.4 5.4 ns t enzh enable-pad z to high 3.8 4.3 5.0 7.1 6.0 ns t enzl enable-pad z to low 4.1 4.7 5.5 7.9 6.6 ns t enhz enable-pad high to z 5.4 6.1 7.2 10.3 8.6 ns t enlz enable-pad low to z 5.4 6.1 7.2 10.3 8.6 ns t glh g-to-pad high 4.2 4.8 5.6 8.0 6.7 ns t ghl g-to-pad low 4.7 5.4 6.3 9.0 7.6 ns t lco i/o latch clock-out (pad-to-pad), 64 clock loading 10.7 11.8 14.2 20.3 17.0 ns t aco array clock-out (pad-to-pad), 64 clock loading 15.0 17.0 20.0 28.6 24.0 ns d tlh capacitive loading, low to high 0.05 0.06 0.07 0.08 0.08 ns/pf d thl capacitive loading, high to low 0.05 0.05 0.06 0.07 0.07 ns/pf
v3.0 31 integrator series fpgas: 1200xl and 3200dx families a1240xl timing characteristics (worst-case commercial conditions, v cc = 4.75 v, t j = 70 c) notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtai ned from the directtime analyzer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se t-up/hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal set-up (hold) time. 5. v cc = 3.0v for 3.3v specifications. ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units logic modulepropagation delays 1 t pd1 single module 2.6 3.0 3.5 5.0 4.2 ns t co sequential clk-to-q 2.6 3.0 3.5 5.0 4.2 ns t go latch g-to-q 2.6 3.0 3.5 5.0 4.2 ns t rs flip-flop (latch) reset-to-q 2.6 3.0 3.5 5.0 4.2 ns predicted routing delays 2 t rd1 fo=1 routing delay 1.1 1.2 1.4 2.0 1.7 ns t rd2 fo=2 routing delay 1.3 1.4 1.7 2.4 2.0 ns t rd3 fo=3 routing delay 1.7 1.9 2.2 3.1 2.6 ns t rd4 fo=4 routing delay 2.3 2.6 3.0 4.3 3.6 ns t rd8 fo=8 routing delay 3.4 3.8 4.5 6.4 5.4 ns sequential timing characteristics 3, 4 t sud flip-flop (latch) data input set-up 0.4 0.4 0.5 0.7 0.6 ns t hd flip-flop (latch) data input hold 0.0 0.0 0.0 0.0 0.0 ns t suena flip-flop (latch) enable set-up 0.8 0.9 1.0 1.4 1.2 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 3.4 3.8 4.5 6.4 5.4 ns t wasyn flip-flop (latch) asynchronous pulse width 3.4 3.8 4.5 6.4 5.4 ns t a flip-flop clock input period 6.8 7.7 9.1 13.0 10.9 ns t inh input buffer latch hold 0.0 0.0 0.0 0.0 0.0 ns t insu input buffer latch set-up 0.3 0.4 0.4 0.6 0.5 ns t outh output buffer latch hold 0.0 0.0 0.0 0.0 0.0 ns t outsu output buffer latch set-up 0.3 0.4 0.4 0.6 0.5 ns f max flip-flop (latch) clock frequency 215 190 160 110 105 mhz
integrator series fpgas: 1200xl and 3200dx families 32 v3.0 a1240xl timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance. ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. units input module propagation delays t inyh pad-to-y high 1.1 1.2 1.4 2.0 1.7 ns t inyl pad-to-y low 1.3 1.4 1.7 2.4 2.0 ns t ingh g-to-y high 2.0 2.3 2.7 3.9 3.2 ns t ingl g-to-y low 2.6 3.0 3.5 5.0 4.2 ns input module predicted routing delays 1 t ird1 fo=1 routing delay 2.9 3.3 3.9 5.6 4.7 ns t ird2 fo=2 routing delay 3.4 3.8 4.5 6.4 5.4 ns t ird3 fo=3 routing delay 3.8 4.3 5.1 7.3 6.1 ns t ird4 fo=4 routing delay 4.1 4.7 5.5 7.9 6.6 ns t ird8 fo=8 routing delay 5.6 6.3 7.4 10.6 8.9 ns global clock network t ckh input low to high fo = 32 fo = 256 5.1 5.7 5.8 6.5 6.8 7.6 9.7 10.9 8.2 9.1 ns ns t ckl input high to low fo = 32 fo = 256 5.0 5.7 5.7 6.5 6.7 7.6 9.6 10.9 8.0 9.1 ns ns t pwh minimum pulse width high fo = 32 fo = 256 2.7 2.9 3.1 3.3 3.6 3.9 5.1 5.6 4.3 4.7 ns ns t pwl minimum pulse width low fo = 32 fo = 256 2.7 2.9 3.1 3.3 3.6 3.9 5.1 5.6 4.3 4.7 ns ns t cksw maximum skew fo = 32 fo = 256 0.8 0.8 0.9 0.9 1.0 1.0 1.4 1.4 1.2 1.2 ns ns t suext input latch external set-up fo = 32 fo = 256 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch external hold fo = 32 fo = 256 2.6 3.2 2.9 3.7 3.4 4.3 4.9 6.1 4.1 5.2 ns ns t p minimum period fo = 32 fo = 256 5.6 6.0 6.3 6.8 7.4 8.0 10.6 11.4 8.9 9.6 ns ns f max maximum frequency fo = 32 fo = 256 215 195 190 170 160 144 110 100 105 95 mhz mhz
v3.0 33 integrator series fpgas: 1200xl and 3200dx families a1240xl timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) note: 1. delays based on 35 pf loading. ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. units ttl output module timing 1 t dlh data-to-pad high 3.8 4.3 5.0 7.1 6.0 ns t dhl data-to-pad low 4.1 4.6 5.4 7.7 6.5 ns t enzh enable-pad z to high 3.8 4.3 5.0 7.1 6.0 ns t enzl enable-pad z to low 4.1 4.7 5.5 7.9 6.6 ns t enhz enable-pad high to z 5.4 6.1 7.2 10.3 8.6 ns t enlz enable-pad low to z 5.4 6.1 7.2 10.3 8.6 ns t glh g-to-pad high 4.2 4.8 5.6 8.0 6.7 ns t ghl g-to-pad low 4.7 5.4 6.3 9.0 7.6 ns t lco i/o latch clock-out (pad-to-pad), 64 clock loading 9.2 10.5 12.3 17.6 14.8 ns t aco array clock-out (pad-to-pad), 64 clock loading 12.9 14.6 17.2 24.6 20.6 ns d tlh capacity loading, low to high 0.04 0.04 0.05 0.06 0.06 ns/pf d thl capacity loading, high to low 0.05 0.06 0.07 0.08 0.08 ns/pf cmos output module timing 1 t dlh data-to-pad high 4.8 5.4 6.4 9.1 7.7 ns t dhl data-to-pad low 3.4 3.8 4.5 6.4 5.4 ns t enzh enable-pad z to high 3.8 4.3 5.0 7.1 6.0 ns t enzl enable-pad z to low 4.1 4.7 5.5 7.9 6.6 ns t enhz enable-pad high to z 5.4 6.1 7.2 10.3 8.6 ns t enlz enable-pad low to z 5.4 6.1 7.2 10.3 8.6 ns t glh g-to-pad high 4.2 4.8 5.6 8.0 6.7 ns t ghl g-to-pad low 4.7 5.4 6.3 9.0 7.6 ns t lco i/o latch clock-out (pad-to-pad), 64 clock loading 10.9 12.4 14.5 20.7 17.4 ns t aco array clock-out (pad-to-pad), 64 clock loading 15.2 17.2 20.3 29.0 24.4 ns d tlh capacity loading, low to high 0.05 0.06 0.07 0.08 0.08 ns/pf d thl capacity loading, high to low 0.05 0.05 0.06 0.07 0.07 ns/pf
integrator series fpgas: 1200xl and 3200dx families 34 v3.0 a3265dx timing characteristics (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtai ned from the directtime analyzer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se t-up/hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal set-up (hold) time. 5. v cc = 3.0v for 3.3v specifications. ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units logic modulepropagation delays 1 combinatorial functions t pd internal array module delay 2.1 2.4 2.9 3.7 3.2 ns t pdd internal decode module delay 2.5 2.8 3.4 4.4 3.7 ns predicted routing delays 2 t rd1 fo=1 routing delay 0.3 0.4 0.5 0.6 0.5 ns t rd2 fo=2 routing delay 0.7 0.8 0.9 1.2 1.0 ns t rd3 fo=3 routing delay 1.0 1.2 1.4 1.8 1.6 ns t rd4 fo=4 routing delay 1.4 1.6 1.9 2.4 2.1 ns t rd5 fo=8 routing delay 2.7 3.2 3.7 4.9 4.1 ns t rdd decode-to-output routing delay 0.46 0.5 0.62 0.8 0.7 ns sequential timing characteristics 3, 4 t co flip-flop clock-to-output 2.3 2.7 3.1 4.1 3.5 ns t go latch gate-to-output 2.1 2.4 2.9 3.7 3.2 ns t sud flip-flop (latch) set-up time 0.35 0.4 0.47 0.6 0.5 ns t hd flip-flop (latch) hold time 0.0 0.0 0.0 0.0 0.0 ns t ro flip-flop (latch) reset to output 2.3 2.7 3.1 4.1 3.5 ns t suena flip-flop (latch) enable set-up 0.75 0.9 1.0 1.3 1.1 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 3.7 4.2 4.9 6.4 5.5 ns t wasyn flip-flop (latch) asynchronous pulse width 4.9 5.5 6.5 8.4 7.1 ns
v3.0 35 integrator series fpgas: 1200xl and 3200dx families a3265dx timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance. ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. units input module propagation delays t inpy input data pad-to-y 1.4 1.6 1.9 2.4 2.1 ns t ingo input latch gate-to-output 3.3 3.7 4.4 5.7 4.8 ns t inh input latch hold 0.0 0.0 0.0 0.0 0.0 ns t insu input latch set-up 0.5 0.6 0.7 0.9 0.8 ns t ila latch active pulse width 5.1 5.9 6.9 9.0 7.7 ns input module predicted routing delays 1 t ird1 fo=1 routing delay 3.2 3.7 4.3 5.6 4.8 ns t ird2 fo=2 routing delay 3.6 4.2 4.9 6.4 5.4 ns t ird3 fo=3 routing delay 3.9 4.5 5.3 6.9 5.9 ns t ird4 fo=4 routing delay 4.5 5.2 6.1 7.9 6.7 ns t ird5 fo=8 routing delay 6.6 7.5 8.8 11.4 9.7 ns t irdd decode-to-output routing delay 0.37 0.4 0.5 0.7 0.6 ns global clock network t ckh input low to high fo=32 fo=256 6.3 7.4 7.1 8.4 8.4 9.9 10.9 12.8 9.2 10.9 ns ns t ckl input high to low fo=32 fo=256 5.9 6.4 6.6 7.3 7.8 8.6 10.1 11.2 8.6 9.5 ns ns t pw minimum pulse width fo=32 fo=256 3.2 3.4 3.7 3.9 4.3 4.6 5.6 6.0 4.8 5.1 ns ns t cksw maximum skew fo=32 fo=256 0.75 0.75 0.9 0.9 1.0 1.0 1.3 1.3 1.1 1.1 ns ns t suext input latch external set-up fo=32 fo=256 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch external hold fo=32 fo=256 2.5 2.5 2.9 2.9 3.4 3.4 4.4 4.4 3.8 3.8 ns ns t p minimum period (1/fmax) fo=32 fo=256 5.0 6.0 7.2 8.3 8.3 9.5 11.9 13.6 9.2 10.6 ns ns f max maximum datapath frequency fo=32 fo=256 173 151 138 121 120 105 84 74 108 95 mhz mhz
integrator series fpgas: 1200xl and 3200dx families 36 v3.0 a3265dx timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) note: 1. delays based on 35pf loading. ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. units ttl output module timing 1 t dlh data-to-pad high 3.8 4.3 5.0 6.5 5.5 ns t dhl data-to-pad low 4.6 5.2 6.1 7.9 6.7 ns t enzh enable-pad z to high 4.8 5.4 6.4 8.3 7.1 ns t enzl enable-pad z to low 5.2 5.9 6.9 9.0 7.6 ns t enhz enable-pad high to z 8.3 9.5 11.1 14.5 12.3 ns t enlz enable-pad low to z 8.3 9.5 11.1 14.5 12.3 ns t glh g-to-pad high 8.3 9.4 11.1 14.4 12.3 ns t ghl g-to-pad low 7.7 8.7 10.2 13.3 11.3 ns t lsu i/o latch output set-up 0.5 0.6 0.7 0.9 0.8 ns t lh i/o latch output hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-out (pad-to-pad) 32 i/o 9.8 11.1 13.1 17.0 14.5 ns t aco array latch clock-out (pad-to-pad)32 i/o 13.9 15.7 18.5 24.1 20.5 ns d tlh capacitive loading, low to high 0.037 0.04 0.05 0.071 0.06 ns/pf d tll capacitive loading, high to low 0.05 0.03 0.07 0.1 0.08 ns/pf t wdo hard-wired wide-decode output 0.3 0.4 0.5 0.7 0.6 ns/pf cmos output module timing 1 t dlh data-to-pad high 4.6 5.2 6.1 7.9 6.7 ns t dhl data-to-pad low 3.8 4.3 5.0 6.5 5.5 ns t enzh enable-pad z to high 4.8 5.5 6.4 8.4 7.1 ns t enzl enable-pad z to low 5.2 5.9 6.9 9.0 7.6 ns t enhz enable-pad high to z 8.3 9.5 11.1 14.5 12.3 ns t enlz enable-pad low to z 8.3 9.5 11.1 14.5 12.3 ns t glh g-to-pad high 8.3 9.4 11.1 14.4 12.3 ns t ghl g-to-pad low 9.0 10.2 12.0 15.6 13.3 ns t lsu i/o latch set-up 0.5 0.6 0.7 0.9 0.8 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-out (pad-to-pad) 32 i/o 11.7 13.3 15.6 20.3 17.3 ns t aco array latch clock-out (pad-to-pad) 32 i/o 16.4 18.5 21.8 28.3 24.1 ns d tlh capacitive loading, low to high 0.05 0.06 0.07 0.1 0.1 ns/pf d tll capacitive loading, high to low 0.04 0.05 0.06 0.1 0.1 ns/pf t wdo hard-wired wide-decode output 0.3 0.4 0.5 0.7 0.6 ns/pf
v3.0 37 integrator series fpgas: 1200xl and 3200dx families a1280xl timing characteristics (worst-case commercial conditions, v cc = 4.75 v, t j = 70 c) notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtai ned from the directtime analyzer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se t-up/hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal set-up (hold) time. 5. v cc = 3.0v for 3.3v specifications. ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed parameter description min. max. min. max. min. max. min. max. min. max. units logic modulepropagation delays 1 t pd1 single module 2.6 3.0 3.5 5.0 4.2 ns t co sequential clk-to-q 2.6 3.0 3.5 5.0 4.2 ns t go latch g-to-q 2.6 3.0 3.5 5.0 4.2 ns t rs flip-flop (latch) reset-to-q 2.6 3.0 3.5 5.0 4.2 ns predicted routing delays 2 t rd1 fo=1 routing delay 1.3 1.4 1.7 2.4 2.0 ns t rd2 fo=2 routing delay 1.8 2.0 2.4 3.4 2.9 ns t rd3 fo=3 routing delay 2.2 2.5 2.9 4.1 3.5 ns t rd4 fo=4 routing delay 2.6 3.0 3.5 5.0 4.2 ns t rd8 fo=8 routing delay 5.0 5.7 6.7 9.6 8.0 ns sequential timing characteristics 3,4 t sud flip-flop (latch) data input set-up 0.4 0.4 0.5 0.7 0.6 ns t hd flip-flop (latch) data input hold 0.0 0.0 0.0 0.0 0.0 ns t suena flip-flop (latch) enable set-up 0.8 0.9 1.0 1.4 1.2 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 3.7 4.3 4.9 7.0 5.9 ns t wasyn flip-flop (latch) asynchronous pulse width 3.7 4.3 4.9 7.0 5.9 ns t a flip-flop clock input period 8.0 8.7 10.0 14.0 12.0 ns t inh input buffer latch hold 0.0 0.0 0.0 0.0 0.0 ns t insu input buffer latch set-up 0.3 0.4 0.4 0.6 0.5 ns t outh output buffer latch hold 0.0 0.0 0.0 0.0 0.0 ns t outsu output buffer latch set-up 0.3 0.4 0.4 0.6 0.5 ns f max flip-flop (latch) clock frequency 200 167 130 90 110 mhz
integrator series fpgas: 1200xl and 3200dx families 38 v3.0 a1280xl timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance. ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. units input module propagation delays t inyh pad-to-y high 1.1 1.2 1.4 2.0 1.7 ns t inyl pad-to-y low 1.3 1.4 1.7 2.4 2.0 ns t ingh g-to-y high 2.0 2.3 2.7 3.9 3.2 ns t ingl g-to-y low 2.6 3.0 3.5 5.0 4.2 ns input module predicted routing delays 1 t ird1 fo=1 routing delay 3.2 3.7 4.3 6.1 5.2 ns t ird2 fo=2 routing delay 3.7 4.2 4.9 7.0 5.9 ns t ird3 fo=3 routing delay 4.0 4.5 5.3 7.6 6.4 ns t ird4 fo=4 routing delay 4.6 5.2 6.1 8.7 7.3 ns t ird8 fo=8 routing delay 6.6 7.5 8.8 12.6 10.6 ns global clock network t ckh input low to high fo = 32 fo = 384 5.1 5.7 5.8 6.5 6.8 7.6 9.7 10.9 8.2 9.1 ns ns t ckl input high to low fo = 32 fo = 384 5.0 5.7 5.7 6.5 6.7 7.6 9.6 10.9 8.0 9.1 ns ns t pwh minimum pulse width high fo = 32 fo = 384 3.2 3.5 3.5 3.9 4.3 4.6 6.1 6.6 5.2 5.5 ns ns t pwl minimum pulse width low fo = 32 fo = 384 3.2 3.5 3.5 3.9 4.3 4.6 6.1 6.6 5.2 5.5 ns ns t cksw maximum skew fo = 32 fo = 384 0.8 0.8 0.9 0.9 1.0 1.0 1.4 1.4 1.2 1.2 ns ns t suext input latch external set-up fo = 32 fo = 384 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch external hold fo = 32 fo = 384 2.6 3.2 2.9 3.7 3.4 4.3 4.9 6.1 4.1 5.2 ns ns t p minimum period fo = 32 fo = 384 6.5 7.2 7.4 8.0 8.7 9.6 12.4 13.7 10.4 11.5 ns ns f max maximum frequency fo = 32 fo = 384 200 180 167 150 143 130 100 90 120 110 mhz mhz
v3.0 39 integrator series fpgas: 1200xl and 3200dx families a1280xl timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) note: 1. delays based on 35 pf loading. ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. units ttl output module timing 1 t dlh data-to-pad high 3.8 4.3 5.0 7.1 6.0 ns t dhl data-to-pad low 4.1 4.6 5.4 7.7 6.5 ns t enzh enable-pad z to high 3.8 4.3 5.0 7.1 6.0 ns t enzl enable-pad z to low 4.1 4.7 5.5 7.7 6.6 ns t enhz enable-pad high to z 5.4 6.1 7.2 10.3 8.6 ns t enlz enable-pad low to z 5.4 6.1 7.2 10.3 8.6 ns t glh g-to-pad high 4.2 4.8 5.6 8.0 6.7 ns t ghl g-to-pad low 4.7 5.4 6.3 9.0 7.6 ns t lco i/o latch clock-out (pad-to-pad), 64 clock loading 9.8 11.0 13.1 18.7 15.7 ns t aco array clock-out (pad-to-pad), 64 clock loading 13.9 15.7 18.5 26.4 22.2 ns d tlh capacitive loading, low to high 0.04 0.04 0.05 0.06 0.06 ns/pf d thl capacitive loading, high to low 0.05 0.06 0.07 0.08 0.08 ns/pf cmos output module timing 1 t dlh data-to-pad high 4.8 5.4 6.4 9.1 7.7 ns t dhl data-to-pad low 3.4 3.8 4.5 6.4 5.4 ns t enzh enable-pad z to high 3.8 4.3 5.0 7.1 6.0 ns t enzl enable-pad z to low 4.1 4.7 5.5 7.9 6.6 ns t enhz enable-pad high to z 5.4 6.1 7.2 10.3 8.6 ns t enlz enable-pad low to z 5.4 6.1 7.2 10.3 8.6 ns t glh g-to-pad high 4.2 4.8 5.6 8.0 6.7 ns t ghl g-to-pad low 4.7 5.4 6.3 9.0 7.6 ns t lco i/o latch clock-out (pad-to-pad), 64 clock loading 11.6 13.0 15.5 22.2 18.6 ns t aco array clock-out (pad-to-pad), 64 clock loading 16.4 18.5 21.8 31.2 26.2 ns d tlh capacitive loading, low to high 0.05 0.06 0.07 0.08 0.08 ns/pf d thl capacitive loading, high to low 0.05 0.05 0.06 0.07 0.07 ns/pf
integrator series fpgas: 1200xl and 3200dx families 40 v3.0 a32100dx timing characteristics (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) ?? 3 speed ?? 2 speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. min. max. units logic modulepropagation delays combinatorial functions t pd internal array module delay 2.2 2.6 3.0 3.5 5.2 4.1 ns t pdd internal decode module delay 2.4 2.7 3.1 3.7 5.7 4.3 ns predicted module routing delays t rd1 fo=1 routing delay 1.0 1.1 1.3 1.5 3.3 1.7 ns t rd2 fo=2 routing delay 1.4 1.7 1.9 2.2 4.3 2.5 ns t rd3 fo=3 routing delay 1.8 2.1 2.5 2.9 5.2 3.4 ns t rd4 fo=4 routing delay 2.4 2.7 3.1 3.7 6.5 4.3 ns t rd5 fo=8 routing delay 4.2 5.0 5.6 6.6 10.0 7.7 ns t rdd decode-to-output routing delay 0.3 0.37 0.4 0.5 0.4 0.6 ns sequential timing characteristics t co flip-flop clock-to-output 2.2 2.6 3.0 3.5 5.0 4.1 ns t go latch gate-to-output 2.2 2.6 3.0 3.5 5.0 4.1 ns t su flip-flop (latch) set-up time 0.3 0.37 0.4 0.5 0.7 0.6 ns t h flip-flop (latch) hold time 0.0 0.0 0.0 0.0 0.0 0.0 ns t ro flip-flop (latch) reset to output 2.2 2.6 3.0 3.5 5.0 4.1 ns t suena flip-flop (latch) enable set-up 0.6 0.75 0.9 1.0 1.4 0.85 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 3.1 3.7 4.2 4.9 7.0 5.7 ns t wasyn flip-flop (latch) asynchronous pulse width 4.1 4.8 5.4 6.4 7.0 7.5 ns
v3.0 41 integrator series fpgas: 1200xl and 3200dx families a32100dx timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) ?? 3 speed ?? 2 speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. min. max. units logic module timing synchronous sram operations t rc read cycle time 6.4 7.5 8.5 10.0 14.3 11.7 ns t wc write cycle time 6.4 7.5 8.5 10.0 14.3 11.7 ns t rckhl clock high/low time 3.2 3.8 4.3 5.0 7.1 5.9 ns t rco data valid after clock high/low 3.2 3.8 4.3 5.0 7.1 5.9 ns t adsu address/data set-up time 1.5 1.8 2.0 2.4 3.4 2.8 ns t adh address/data hold time 0.0 0.0 0.0 0.0 0.0 0.0 ns t rensu read enable set-up 0.6 0.7 0.8 0.9 1.3 1.0 ns t renh read enable hold 3.2 3.8 4.3 5.0 7.1 5.9 ns t wensu write enable set-up 2.6 3.0 3.4 4.0 5.7 4.7 ns t wenh write enable hold 0.0 0.0 0.0 0.0 0.0 0.0 ns t bens block enable set-up 2.6 3.1 3.5 4.1 5.8 4.8 ns t benh block enable hold 0.0 0.0 0.0 0.0 0.0 0.0 ns asynchronous sram operations t rpd asynchronous access time 7.7 9.0 10.2 12.0 17.2 14.1 ns t rdadv read address valid 8.3 9.8 11.1 13.0 18.6 15.2 ns t adsu address/data set-up time 1.5 1.8 2.0 2.4 3.4 2.8 ns t adh address/data hold time 0.0 0.0 0.0 0.0 0.0 0.0 ns t rensua read enable set-up to address valid 0.57 0.7 0.8 0.9 1.3 1.0 ns t renha read enable hold 3.2 3.8 4.3 5.0 7.1 5.9 ns t wensu write enable set-up 2.6 3.0 3.4 4.0 5.7 4.7 ns t wenh write enable hold 0.0 0.0 0.0 0.0 0.0 0.0 ns t doh data out hold time 1.1 1.35 1.5 1.8 2.6 2.1 ns
integrator series fpgas: 1200xl and 3200dx families 42 v3.0 a32100dx timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance. ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. min. max. units input module propagation delays t inpy input data pad-to-y 1.4 1.65 1.9 2.2 3.1 2.5 ns t ingo input latch gate-to-output 1 2.9 3.4 3.8 4.5 6.4 5.3 ns t inh input latch hold 1 0.0 0.0 0.0 0.0 0.0 0.0 ns t insu input latch set-up 1 0.45 0.5 0.6 0.7 1.0 0.82 ns t ila latch active pulse width 1 4.4 4.8 5.9 6.9 9.8 8.1 ns input module predicted routing delays t ird1 fo=1 routing delay 1.6 1.75 2.1 2.5 3.6 2.9 ns t ird2 fo=2 routing delay 2.0 2.4 2.7 3.2 4.6 3.8 ns t ird3 fo=3 routing delay 2.6 3.0 3.4 4.0 5.7 4.7 ns t ird4 fo=4 routing delay 2.6 3.0 3.4 4.0 5.7 4.7 ns t ird8 fo=8 routing delay 4.1 4.8 5.4 6.4 9.1 7.5 ns global clock network t ckh input low to high fo=32 fo=635 4.7 5.7 5.6 6.75 6.3 7.7 7.4 9.0 10.5 12.8 8.7 10.5 ns ns t ckl input high to low fo=32 fo=635 4.8 6.4 5.6 7.5 6.4 8.5 7.5 10.0 10.7 14.2 8.8 11.7 ns ns t pwh minimum pulse width high fo=32 fo=635 2.5 2.7 2.9 3.2 3.3 3.7 3.9 4.3 5.6 6.1 4.5 5.0 ns ns t pwl minimum pulse width low fo=32 fo=635 2.5 2.7 2.9 3.2 3.3 3.7 3.9 4.3 5.5 6.1 4.5 5.0 ns ns t cksw maximum skew fo=32 fo=635 0.6 0.6 0.75 0.75 0.9 0.9 1.0 1.0 1.4 1.4 1.8 1.8 ns ns t suext input latch external set-up fo=32 fo=635 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch external hold fo=32 fo=635 2.2 2.7 2.5 3.2 2.9 3.7 3.4 4.3 4.9 6.1 4.0 6.1 ns ns t p minimum period (1/fmax) fo=32 fo=635 5.0 5.5 6.0 6.4 7.4 8.2 7.9 8.6 12.4 13.7 9.3 10.1 ns ns f hmax maximum datapath frequency fo=32 fo=635 183 167 159 145 146 133 127 116 89 81 108 99 mhz mhz
v3.0 43 integrator series fpgas: 1200xl and 3200dx families a32100dx timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance. ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. min. max. units ttl output module timing 1 t dlh data-to-pad high 3.7 4.3 4.9 5.8 8.2 6.8 ns t dhl data-to-pad low 4.5 5.3 6.0 7.1 10.1 8.3 ns t enzh enable-pad z to high 4.8 5.6 6.4 7.5 10.7 8.8 ns t enzl enable-pad z to low 5.1 6.0 6.8 8.0 11.4 9.4 ns t enhz enable-pad high to z 8.3 9.8 11.1 13.0 18.5 15.2 ns t enlz enable-pad low to z 8.3 9.8 11.1 13.0 18.5 15.2 ns t glh g-to-pad high 8.3 9.8 11.1 13.0 18.5 15.2 ns t ghl g-to-pad low 9.0 10.5 12.0 14.1 20.1 16.4 ns t lsu i/o latch output set-up 0.26 0.3 0.34 0.4 0.6 0.6 ns t lh i/o latch output hold 0.0 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-out (pad-to-pad) 32 i/o 8.4 9.8 11.1 13.1 18.7 15.3 ns t aco array latch clock-out (pad-to-pad) 32 i/o 11.8 13.8 15.7 18.5 26.5 21.7 ns d tlh capacitive loading, low to high 0.03 0.037 0.04 0.05 0.07 0.06 ns/pf d thl capacitive loading, high to low 0.04 0.05 0.06 0.07 0.10 0.08 ns/pf t wdo hard-wired wide-decode output 0.04 0.045 0.05 0.06 0.09 0.07 ns cmos output module timing 1 t dlh data-to-pad high 4.5 5.3 6.0 7.1 10.1 8.3 ns t dhl data-to-pad low 3.7 4.3 4.9 5.8 8.2 6.8 ns t enzh enable-pad z to high 4.8 5.6 6.4 7.5 10.7 8.8 ns t enzl enable-pad z to low 5.1 6.0 6.8 8.0 11.4 9.4 ns t enhz enable-pad high to z 8.3 9.8 11.1 13.0 18.5 15.2 ns t enlz enable-pad low to z 8.3 9.8 11.1 13.0 18.5 15.2 ns t glh g-to-pad high 8.3 9.8 11.1 13.0 18.5 15.2 ns t ghl g-to-pad low 9.0 10.5 12.0 14.1 20.0 16.4 ns t lsu i/o latch set-up 0.26 0.3 0.3 0.4 0.6 0.6 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-out (pad-to-pad) 32 i/o 9.9 11.0 13.2 15.5 22.3 18.2 ns t aco array latch clock-out (pad-to-pad) 32 i/o 13.9 16.4 18.5 21.8 30.0 25.6 ns d tlh capacitive loading, low to high 0.04 0.052 0.05 0.07 0.10 0.08 ns/pf d thl capacitive loading, high to low 0.04 0.045 0.05 0.06 0.09 0.07 ns/pf t wdo hard-wired wide-decode output 0.04 0.045 0.05 0.06 0.09 0.07 ns
integrator series fpgas: 1200xl and 3200dx families 44 v3.0 a32140dx timing characteristics (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtai ned from the directtime analyzer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se t-up/hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal set-up (hold) time. ?? 2 speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. units logic module propagation delays 1 combinatorial functions t pd internal array module delay 1.8 2.3 2.8 3.6 3.2 ns t pdd internal decode module delay 1.9 2.5 3.0 3.8 3.5 ns predicted routing delays 2 t rd1 fo=1 routing delay 1.0 1.3 1.6 2.0 1.8 ns t rd2 fo=2 routing delay 1.4 1.9 2.2 2.8 2.5 ns t rd3 fo=3 routing delay 1.8 2.4 2.8 3.7 3.3 ns t rd4 fo=4 routing delay 2.2 2.9 3.4 4.5 4.0 ns t rd5 fo=8 routing delay 3.8 5.0 5.9 7.7 7.0 ns t rdd decode-to-output routing delay 0.5 0.7 0.78 1.0 0.91 ns sequential timing characteristics 3, 4 t co flip-flop clock-to-output 2.1 2.8 3.3 4.3 3.9 ns t go latch gate-to-output 1.8 2.3 2.8 3.6 3.2 ns t su flip-flop (latch) set-up time 0.3 0.4 0.47 0.6 0.55 ns t h flip-flop (latch) hold time 0.0 0.0 0.0 0.0 0.0 ns t ro flip-flop (latch) reset to output 2.1 2.8 3.3 4.3 3.9 ns t suena flip-flop (latch) enable set-up 0.6 0.9 1.0 1.3 1.17 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 2.6 3.5 4.1 5.4 4.82 ns t wasyn flip-flop (latch) asynchronous pulse width 4.15.56.58.47.6 ns
v3.0 45 integrator series fpgas: 1200xl and 3200dx families a32140dx timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance. ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. units input module propagation delays t inpy input data pad-to-y 1.2 1.6 1.9 2.4 2.2 ns t ingo input latch gate-to-output 2.3 3.1 3.7 4.7 4.3 ns t inh input latch hold 0.0 0.0 0.0 0.0 0.0 ns t insu input latch set-up 0.3 0.4 0.47 0.6 0.55 ns t ila latch active pulse width 3.1 4.2 4.9 6.4 5.7 ns input module predicted routing delays 1 t ird1 fo=1 routing delay 2.7 3.7 4.3 5.6 5.0 ns t ird2 fo=2 routing delay 3.1 4.2 4.9 6.4 5.7 ns t ird3 fo=3 routing delay 3.4 4.5 5.3 6.9 6.2 ns t ird4 fo=4 routing delay 3.9 5.2 6.1 7.9 7.1 ns t ird5 fo=8 routing delay 5.6 7.5 8.8 11.4 10.3 ns t irdd decode-to-output routing delay 0.3 0.4 0.5 0.7 0.6 ns global clock network t ckh input low to high fo=32 fo=486 6.2 6.8 8.3 9.1 9.7 10.7 12.7 13.9 11.4 12.5 ns ns t ckl input high to low fo=32 fo=486 6.12 6.7 8.2 8.9 9.6 10.5 12.5 13.6 11.3 12.3 ns ns t pw minimum pulse width fo=32 fo=486 2.7 2.9 3.7 3.9 4.3 4.6 5.6 6.0 5.0 5.41 ns ns t cksw maximum skew fo=32 fo=486 0.6 0.6 0.9 0.9 1.0 1.0 1.3 1.3 1.17 1.17 ns ns t suext input latch external set-up fo=32 fo=486 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch external hold fo=32 fo=486 2.2 2.2 2.9 2.9 3.4 3.4 4.4 4.4 4.0 4.0 ns ns t p minimum period (1/fmax) fo=32 fo=486 5.7 6.6 7.6 8.3 8.3 9.5 11.9 13.6 9.0 11.1 ns ns f max maximum datapath frequency fo=32 fo=486 173 151 138 121 120 105 84 74 102 90 mhz mhz
integrator series fpgas: 1200xl and 3200dx families 46 v3.0 a32140dx timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) note: 1. delays based on 35 pf loading. ?? 2 speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. units ttl output module timing 1 t dlh data-to-pad high 3.3 4.4 5.1 6.7 6.0 ns t dhl data-to-pad low 3.5 4.6 5.4 7.1 6.3 ns t enzh enable-pad z to high 4.1 5.5 6.4 8.4 7.5 ns t enzl enable-pad z to low 4.4 5.9 6.9 9.0 8.1 ns t enhz enable-pad high to z 7.1 9.5 11.1 14.5 13.0 ns t enlz enable-pad low to z 7.1 9.5 11.1 14.5 13.0 ns t glh g-to-pad high 6.5 8.7 10.2 13.3 12.0 ns t ghl g-to-pad low 6.5 8.7 10.2 13.3 12.0 ns t lsu i/o latch output set-up 0.4 0.6 0.7 0.9 0.82 ns t lh i/o latch output hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-out (pad-to-pad) 32 i/o 8.4 11.1 13.1 17.0 15.4 ns t aco array latch clock-out (pad-to-pad) 32 i/o 11.8 15.7 18.5 24.1 21.7 ns d tlh capacitive loading, low to high 0.03 0.04 0.05 0.07 0.06 ns/pf d thl capacitive loading, high to low 0.02 0.03 0.07 0.1 0.08 ns/pf t wdo hard-wired wide-decode output 0.03 0.04 0.05 0.07 0.06 ns/pf cmos output module timing 1 t dlh data-to-pad high 3.5 4.6 5.4 7.1 6.0 ns t dhl data-to-pad low 3.3 4.4 5.1 6.7 6.3 ns t enzh enable-pad z to high 4.1 5.5 6.4 8.4 7.5 ns t enzl enable-pad z to low 4.4 5.9 6.9 9.0 8.1 ns t enhz enable-pad high to z 7.1 9.5 11.1 14.5 13.0 ns t enlz enable-pad low to z 7.1 9.5 11.1 14.5 13.0 ns t glh g-to-pad high 6.5 8.7 10.2 13.3 12.0 ns t ghl g-to-pad low 6.5 8.7 10.2 13.3 12.0 ns t lsu i/o latch set-up 0.4 0.6 0.7 0.9 0.82 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-out (pad-to-pad) 32 i/o 9.9 13.3 15.6 20.3 18.3 ns t aco array latch clock-out (pad-to-pad) 32 i/o 13.9 18.5 21.8 28.3 25.6 ns d tlh capacitive loading, low to high 0.04 0.06 0.07 0.1 0.08 ns/pf d thl capacitive loading, high to low 0.04 0.05 0.06 0.1 0.07 ns/pf t wdo hard-wired wide-decode output 0.3 0.4 0.5 0.7 0.6 ns/pf
v3.0 47 integrator series fpgas: 1200xl and 3200dx families a32200dx timing characteristics (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) ?? 3 speed ?? 2 speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. min. max. units logic module propagation delays combinatorial functions t pd internal array module delay 2.0 2.4 2.7 3.2 4.5 3.7 ns t pdd internal decode module delay 2.5 2.9 3.3 3.9 5.6 4.5 ns predicted module routing delays t rd1 fo=1 routing delay 1.1 1.35 1.5 1.8 2.6 2.1 ns t rd2 fo=2 routing delay 1.7 2.0 2.2 2.6 3.7 3.0 ns t rd3 fo=3 routing delay 2.1 2.4 2.8 3.3 4.7 3.8 ns t rd4 fo=4 routing delay 2.6 3.0 3.4 4.0 5.7 4.7 ns t rd5 fo=8 routing delay 4.5 5.3 6.0 7.0 10.0 8.2 ns t rdd decode-to-output routing delay 0.6 0.67 0.8 0.9 1.3 1.0 ns sequential timing characteristics t co flip-flop clock-to-output 2.3 2.7 3.1 3.6 5.1 4.2 ns t go latch gate-to-output 2.0 2.4 2.7 3.2 4.5 3.7 ns t su flip-flop (latch) set-up time 0.3 0.35 0.4 0.47 0.7 0.55 ns t h flip-flop (latch) hold time 0.0 0.0 0.0 0.0 0.0 0.0 ns t ro flip-flop (latch) reset to output 2.3 2.7 3.1 3.6 5.1 4.2 ns t suena flip-flop (latch) enable set-up 0.6 0.75 0.9 1.0 1.4 1.17 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 3.1 3.7 4.2 4.9 7.0 5.7 ns t wasyn flip-flop (latch) asynchronous pulse width 4.1 4.9 5.5 6.5 9.2 7.6 ns
integrator series fpgas: 1200xl and 3200dx families 48 v3.0 a32200dx timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) ?? 3 speed ?? 2 speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. min. max. units logic module timing synchronous sram operations t rc read cycle time 6.4 7.5 8.5 10.0 14.3 11.7 ns t wc write cycle time 6.4 7.5 8.5 10.0 14.3 11.7 ns t rckhl clock high/low time 3.2 3.9 4.3 5.0 7.1 5.8 ns t rco data valid after clock high/low 3.2 3.8 4.3 5.0 7.1 5.8 ns t adsu address/data set-up time 1.5 1.8 2.0 2.4 3.4 2.8 ns t adh address/data hold time 0.0 0.0 0.0 0.0 0.0 0.0 ns t rensu read enable set-up 0.6 0.7 0.8 0.9 1.4 1.0 ns t renh read enable hold 3.2 3.8 4.3 5.0 7.0 5.8 ns t wensu write enable set-up 2.6 3.0 3.4 4.0 5.4 4.7 ns t wenh write enable hold 0.0 0.0 0.0 0.0 0.0 0.0 ns t bens block enable set-up 2.6 3.1 3.5 4.1 5.6 4.8 ns t benh block enable hold 0.0 0.0 0.0 0.0 0.0 0.0 ns asynchronous sram operations t rpd asynchronous access time 7.7 9.0 10.2 12.0 17.2 14.1 ns t rdadv read address valid 8.3 9.75 11.1 13.0 18.6 15.2 ns t adsu address/data set-up time 1.5 1.8 2.0 2.4 3.4 2.8 ns t adh address/data hold time 0.0 0.0 0.0 0.0 0.0 0.0 ns t rensu read enable set-up to address valid 0.57 0.7 0.8 0.9 1.4 1.0 ns t renha read enable hold 3.2 3.8 4.3 5.0 7.1 5.8 ns t wensu write enable set-up 2.6 3.0 3.4 4.0 5.4 4.7 ns t wenh write enable hold 0.0 0.0 0.0 0.0 0.0 0.0 ns t doh data out hold time 1.1 1.3 1.5 1.8 2.6 2.1 ns
v3.0 49 integrator series fpgas: 1200xl and 3200dx families a32200dx timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance. ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. min. max. units input module propagation delays t inpy input data pad-to-y 1.4 1.65 1.9 2.2 2.9 2.5 ns t ingo input latch gate-to-output 1 3.3 3.2 4.3 5.1 7.3 6.0 ns t inh input latch hold 1 0.0 0.0 0.0 0.0 0.0 0.0 ns t insu input latch set-up 1 0.45 0.52 0.6 0.7 1.0 0.8 ns t ila latch active pulse width 1 4.4 5.2 5.9 6.9 9.8 8.1 ns input module predicted routing delays t ird1 fo=1 routing delay 1.9 2.2 2.6 3.0 4.2 3.5 ns t ird2 fo=2 routing delay 2.5 2.9 3.3 3.9 5.5 4.5 ns t ird3 fo=3 routing delay 3.3 3.9 4.4 5.2 7.6 6.1 ns t ird4 fo=4 routing delay 3.9 4.5 5.2 6.1 8.7 7.1 ns t ird5 fo=8 routing delay 5.0 6.0 6.7 7.9 11.2 9.3 ns t irdd decode-to-output delay 0.3 0.37 0.4 0.5 0.7 0.6 ns global clock network t ckh input low to high fo=32 fo=635 5.3 6.1 6.2 7.2 7.1 8.2 8.3 9.6 11 .8 13.7 9.7 11 .3 ns ns t ckl input high to low fo=32 fo=635 5.2 6.8 6.2 8.0 7.0 9.0 8.2 10.6 11 .7 15.1 9.6 12.8 ns ns t pwh minimum pulse width high fo=32 fo=635 2.7 2.9 3.2 3.45 3.7 3.9 4.3 4.6 6.1 6.6 5.0 5.4 ns ns t pwl minimum pulse width low fo=32 fo=635 2.7 2.9 3.2 3.45 3.7 3.9 4.3 4.6 6.1 6.6 5.0 5.4 ns ns t cksw maximum skew fo=32 fo=635 0.6 0.6 0.75 0.75 0.9 0.9 1.0 1.0 1.4 1.4 1.1 1.1 ns ns t suext input latch external set-up fo=32 fo=635 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch external hold fo=32 fo=635 2.2 2.7 2.6 3.2 2.9 3.7 3.4 4.3 4.9 6.1 4.0 5.0 ns ns t p minimum period (1/fmax) fo=32 fo=635 5.5 6.1 6.5 7.2 7.4 8.2 8.7 9.6 12.4 13.7 10.2 11 .2 ns ns f hmax maximum datapath frequency fo=32 fo=635 165 151 153. 140 132 121 11 5 105 80 73 98 90 mhz mhz
integrator series fpgas: 1200xl and 3200dx families 50 v3.0 a32200dx timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance. ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. min. max. units ttl output module timing 1 t dlh data-to-pad high 3.7 4.3 4.9 5.8 8.3 6.8 ns t dhl data-to-pad low 4.5 5.3 6.0 7.1 10.1 8.3 ns t enzh enable-pad z to high 4.8 5.6 6.4 7.5 10.7 8.8 ns t enzl enable-pad z to low 5.2 6.0 6.9 8.1 11.5 9.5 ns t enhz enable-pad high to z 8.3 9.7 11.1 13.0 18.5 15.2 ns t enlz enable-pad low to z 8.3 9.7 11.1 13.0 18.5 15.2 ns t glh g-to-pad high 8.3 9.7 11.1 13.0 18.5 15.2 ns t ghl g-to-pad low 8.9 10.5 11.9 14.0 20.0 16.5 ns t lsu i/o latch output set-up 0.26 0.3 0.3 0.4 0.6 0.5 ns t lh i/o latch output hold 0.0 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-out (pad-to-pad) 32 i/o 8.4 9.8 11.1 13.1 18.7 15.4 ns t aco array latch clock-out (pad-to-pad) 32 i/o 11.8 13.9 15.7 18.5 26.5 21.7 ns d tlh capacitive loading, low to high 0.03 0.035 0.04 0.05 0.07 0.06 ns/pf d thl capacitive loading, high to low 0.04 0.05 0.06 0.07 0.10 0.08 ns/pf t wdo hard-wired wide-decode output 0.04 0.045 0.05 0.06 0.09 0.07 ns cmos output module timing 1 t dlh data-to-pad high 4.5 5.3 6.0 5.8 8.3 6.8 ns t dhl data-to-pad low 3.7 4.3 4.9 7.1 10.1 8.3 ns t enzh enable-pad z to high 4.8 5.6 6.4 7.5 10.7 8.8 ns t enzl enable-pad z to low 5.2 6.0 6.9 8.1 11.5 9.5 ns t enhz enable-pad high to z 8.3 9.7 11.1 13.0 18.5 15.2 ns t enlz enable-pad low to z 8.3 9.7 11.1 13.0 18.5 15.2 ns t glh g-to-pad high 8.3 9.7 11.1 13.0 18.5 15.2 ns t ghl g-to-pad low 8.9 10.5 11.9 14.0 20.0 16.5 ns t lsu i/o latch set-up 0.26 0.3 0.3 0.4 0.6 0.5 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-out (pad-to-pad) 32 i/o 9.9 11.6 13.2 15.5 22.3 18.2 ns t aco array latch clock-out (pad-to-pad) 32 i/o 13.9 16.3 18.5 21.8 31.2 25.6 ns d tlh capacitive loading, low to high 0.04 0.05 0.06 0.07 0.10 0.08 ns/pf d thl capacitive loading, high to low 0.04 0.045 0.05 0.06 0.09 0.07 ns/pf t wdo hard-wired wide-decode output 0.04 0.045 0.05 0.06 0.09 0.07 ns
v3.0 51 integrator series fpgas: 1200xl and 3200dx families a32300dx timing characteristics (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) ?? 3 speed ?? 2 speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. min. max. units logic module propagation delays combinatorial functions t pd internal array module delay 2.2 2.6 2.9 3.4 4.8 4.0 ns t pdd internal decode module delay 2.5 2.9 3.3 3.9 5.6 4.5 ns predicted module routing delays t rd1 fo=1 routing delay 1.1 1.4 1.5 1.8 2.5 2.1 ns t rd2 fo=2 routing delay 1.7 2.0 2.3 2.7 3.8 3.2 ns t rd3 fo=3 routing delay 2.4 2.8 3.1 3.7 5.2 4.3 ns t rd4 fo=4 routing delay 2.9 3.6 3.9 4.6 6.5 5.4 ns t rd5 fo=8 routing delay 5.2 6.2 7.0 8.2 10.0 9.6 ns t rdd decode-to-output routing delay 0.6 0.7 0.8 0.9 1.3 1.0 ns sequential timing characteristics t co flip-flop clock-to-output 2.3 2.7 3.1 3.6 5.0 4.2 ns t go latch gate-to-output 2.2 2.6 2.9 3.4 4.5 4.0 ns t su flip-flop (latch) set-up time 0.32 0.4 0.42 0.5 0.7 0.6 ns t h flip-flop (latch) hold time 0.0 0.0 0.0 0.0 0.0 0.0 ns t ro flip-flop (latch) reset to output 2.2 2.6 3.0 3.5 5.0 4.1 ns t suena flip-flop (latch) enable set-up 0.6 0.75 0.9 1.0 1.4 1.1 ns t hena flip-flop (latch) enable hold 0.0 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 3.1 3.7 4.2 4.9 7.0 5.7 ns t wasyn flip-flop (latch) asynchronous pulse width 3.5 4.1 4.7 5.5 7.9 6.4 ns
integrator series fpgas: 1200xl and 3200dx families 52 v3.0 a32300dx timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) ?? 3 speed ?? 2 speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. min. max. units logic module timing synchronous sram operations t rc read cycle time 6.4 7.5 8.5 10.0 14.3 11.6 ns t wc write cycle time 6.4 7.5 8.5 10.0 14.3 11.6 ns t rckhl clock high/low time 3.2 3.75 4.3 5.0 7.1 5.8 ns t rco data valid after clock high/low 3.2 3.75 4.3 5.0 7.1 5.8 ns t adsu address/data set-up time 1.5 1.8 2.0 2.4 3.4 2.82 ns t adh address/data hold time 0.0 0.0 0.0 0.0 0.0 0.0 ns t rensu read enable set-up 0.6 0.68 0.8 0.9 1.3 1.05 ns t renh read enable hold 3.2 3.75 4.3 5.0 7.1 5.8 ns t wensu write enable set-up 2.6 3.0 3.4 4.0 5.7 4.7 ns t wenh write enable hold 0.0 0.0 0.0 0.0 0.0 0.0 ns t bens block enable set-up 2.6 2.3 3.5 4.1 5.9 4.8 ns t benh block enable hold 0.0 0.0 0.0 0.0 0.0 0.0 ns asynchronous sram operations t rpd asynchronous access time 7.7 9.0 10.2 12.0 17.2 14.1 ns t rdadv read address valid 8.3 9.6 11.1 13.0 18.6 15.2 ns t adsu address/data set-up time 1.5 1.8 2.0 2.4 3.4 2.8 ns t adh address/data hold time 0.0 0.0 0.0 0.0 0.0 0.0 ns t rensua read enable set-up to address valid 0.57 0.68 0.8 0.9 1.3 1.05 ns t renha read enable hold 3.2 3.75 4.3 5.0 7.1 5.8 ns t wensu write enable set-up 2.6 3.0 3.4 4.0 5.7 4.7 ns t wenh write enable hold 0.0 0.0 0.0 0.0 0.0 0.0 ns t doh data out hold time 1.1 1.35 1.5 1.8 2.6 2.1 ns
v3.0 53 integrator series fpgas: 1200xl and 3200dx families a32300dx timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance. ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. min. max. units input module propagation delays t inpy input data pad-to-y 1.4 1.7 1.9 2.2 3.1 2.5 ns t ingo input latch gate-to-output 1 2.93.43.84.56.45.2ns t inh input latch hold 1 0.0 0.0 0.0 0.0 0.0 0.0 ns t insu input latch set-up 1 0.45 0.5 0.6 0.7 1.0 0.82 ns t ila latch active pulse width 1 4.4 5.2 5.9 6.9 9.8 8.1 ns input module predicted routing delays t ird1 fo=1 routing delay 1.9 2.3 2.6 3.0 4.2 3.5 ns t ird2 fo=2 routing delay 2.5 2.9 3.3 3.9 5.5 4.6 ns t ird3 fo=3 routing delay 3.3 3.9 4.4 5.2 7.4 6.1 ns t ird4 fo=4 routing delay 3.9 4.6 5.2 6.1 8.7 7.2 ns t ird5 fo=8 routing delay 5.0 6.0 6.7 7.9 11.2 9.2 ns t rdd decode-to-output routing delay 0.6 0.67 0.8 0.9 1.3 1.05 ns global clock network t ckh input low to high fo=32 fo=635 6.4 7.3 7.6 8.6 8.6 9.7 10.1 11 .4 14.4 16.2 11 .8 13.4 ns ns t ckl input high to low fo=32 fo=635 6.6 7.1 7.7 8.4 8.8 9.5 10.3 11 .2 14.7 16.0 12.1 13.1 ns ns t pwh minimum pulse width high fo=32 fo=635 3.0 3.3 3.5 3.8 4.0 4.3 4.7 5.1 6.7 7.2 5.5 6.0 ns ns t pwl minimum pulse width low fo=32 fo=635 3.0 3.3 3.8 3.8 4.0 4.3 4.7 5.1 6.7 7.2 5.5 6.0 ns ns t cksw maximum skew fo=32 fo=635 0.6 0.6 0.75 0.75 0.9 0.9 1.0 1.0 1.4 1.4 1.17 1.17 ns ns t suext input latch external set-up fo=32 fo=635 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns t hext input latch external hold fo=32 fo=635 2.2 2.7 2.6 3.2 2.9 3.7 3.4 4.3 4.9 6.1 4.0 5.0 ns ns t p minimum period (1/fmax) fo=32 fo=635 5.5 6.1 6.9 7.7 7.4 8.2 9.3 10.2 13.2 14.5 10.9 12.0 ns ns f hmax maximum datapath frequency fo=32 fo=635 154 141 142 130 123 113 107 98 75 69 91 83 mhz mhz
integrator series fpgas: 1200xl and 3200dx families 54 v3.0 a32300dx timing characteristics (continued) (worst-case commercial conditions v cc = 4.75 v, t j = 70 c) note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual performance. ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed ?? f ? speed 3.3v ? std ? speed parameter description min. max. min. max. min. max. min. max. min. max. min. max. units ttl output module timing 1 t dlh data-to-pad high 3.7 4.3 4.9 5.8 7.7 8.2 ns t dhl data-to-pad low 4.4 5.2 5.9 6.9 8.1 9.8 ns t enzh enable-pad z to high 4.8 5.6 6.4 7.5 8.8 10.7 ns t enzl enable-pad z to low 5.1 6.0 6.8 8.0 9.4 11.4 ns t enhz enable-pad high to z 8.3 9.75 11.1 13.0 15.2 18.5 ns t enlz enable-pad low to z 8.3 9.75 11.1 13.0 15.2 18.5 ns t glh g-to-pad high 4.3 5.0 5.7 6.7 7.9 9.6 ns t ghl g-to-pad low 5.4 6.3 7.1 8.4 7.9 12.0 ns t lsu i/o latch output set-up 0.26 0.3 0.34 0.4 0.47 0.6 ns t lh i/o latch output hold 0.0 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-out (pad-to-pad) 32 i/o 8.4 9.7 11.1 13.1 15.4 18.7 ns t aco array latch clock-out (pad-to-pad) 32 i/o 11.8 13.9 15.7 18.5 21.8 26.5 ns d tlh capacitive loading, low to high 0.26 0.3 0.34 0.4 0.47 0.6 ns/pf d thl capacitive loading, high to low 0.32 0.37 0.4 0.5 0.58 0.7 ns/pf t wdo hard-wired wide-decode output 0.03 0.037 0.04 0.05 0.058 0.07 ns cmos output module timing 1 t dlh data-to-pad high 4.4 5.2 5.9 6.9 8.1 8.2 ns t dhl data-to-pad low 3.7 4.3 4.9 5.8 7.7 9.8 ns t enzh enable-pad z to high 4.8 5.6 6.4 7.5 8.8 10.7 ns t enzl enable-pad z to low 5.1 6.0 6.8 8.0 9.4 11.4 ns t enhz enable-pad high to z 8.3 9.75 11.1 13.0 15.2 18.5 ns t enlz enable-pad low to z 8.3 9.75 11.1 13.0 15.2 18.5 ns t glh g-to-pad high 4.3 5.0 5.7 6.7 7.9 9.6 ns t ghl g-to-pad low 5.4 6.3 7.1 8.4 9.9 12.0 ns t lsu i/o latch set-up 0.26 0.3 0.34 0.4 0.47 0.6 ns t lh i/o latch hold 0.0 0.0 0.0 0.0 0.0 0.0 ns t lco i/o latch clock-out (pad-to-pad) 32 i/o 9.9 11.6 13.2 15.5 17.6 22.3 ns t aco array latch clock-out (pad-to-pad) 32 i/o 13.9 16.4 18.5 21.8 25.6 31.2 ns d tlh capacitive loading, low to high 0.32 0.37 0.4 0.5 0.6 0.10 ns/pf d thl capacitive loading, high to low 0.26 0.3 0.3 0.4 0.5 0.09 ns/pf t wdo hard-wired wide-decode output 0.03 0.037 0.04 0.05 0.06 0.09 ns
v3.0 55 integrator series fpgas: 1200xl and 3200dx families pin descriptions clka, clkb clock a and clock b (input) ttl clock inputs for clock distribution networks. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. dclk diagnostic clock (input) ttl clock input for diagnostic probe and device programming. dclk is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. gnd ground (input) input low supply voltage. i/o input/output (input, output) i/o pin functions as an input, output, three-state or bidirectional buffer. input and output levels are compatible with standard ttl and cmos specifications. unused i/o pins are automatically driven low by the designer series software for xl devices and are automatically tristated for dx devices. mode mode (input) the mode pin controls the use of multi-function pins (dclk, pra, prb, sdi, tdo). when the mode pin is high, the special functions are active. to provide actionprobe capability, the mode pin should be terminated to gnd through a 10k resistor so the mode pin can be pulled high when required. nc no connection this pin is not connected to circuitry within the device. these pins can be driven to any voltage or can be left floating with no effect on the operation of the device. pra, i/o probe a (output) the probe a pin is used to output data from any user-defined design node within the device. this independent diagnostic pin is used in conjunction with the probe b pin to allow real-time diagnostic output of any signal path within the device. the probe a pin can be used as a user-defined i/o when debugging has been completed. the pin ? s probe capabilities can be permanently disabled to protect programmed design confidentiality. pra is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. prb, i/o probe b (output) the probe b pin is used to output data from any user-defined design node within the device. this independent diagnostic pin is used in conjunction with the probe a pin to allow real-time diagnostic output of any signal path within the device. the probe b pin can be used as a user-defined i/o when debugging has been completed. the pin ? s probe capabilities can be permanently disabled to protect programmed design confidentiality. prb is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. qclka,b,c,d quadrant clock (input/output) these four pins are the quadrant clock inputs. when not used as a register control signal, these pins can function as general purpose i/o. sdo serial data (output) serial data output for diagnostic probe and device programming. sdo is active when the mode pin is high. this pin functions as an i/o when mode pin is low. sdi serial data input (input) serial data input for diagnostic probe and device programming. sdi is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. tck test clock clock signal to shift the jtag data into the device. this pin functions as an i/o when the jtag fuse is not programmed. tdi test data in serial data input for jtag instructions and data. data is shifted in on the rising edge of tclk. this pin functions as an i/o when the jtag fuse is not programmed. tdo test data out serial data output for jtag instructions and test data. this pin functions as an i/o when the jtag fuse is not programmed. tms test mode select serial data input for jtag test mode. data is shifted in on the rising edge of tclk. this pin functions as an i/o when the jtag fuse is not programmed. v cc supply voltage (input) input high supply voltage. note: tck, tdi, tdo, tms are only available on devices containing jtag circuitry.
integrator series fpgas: 1200xl and 3200dx families 56 v3.0 package pin assignments 84-pin plcc package (top view) 184 84-pin plcc
v3.0 57 integrator series fpgas: 1200xl and 3200dx families notes: 1. i/o (wd): denotes i/o pin with an associated wide-decode module 2. wide-decode i/o (wd) can also be general purpose user i/o. 3. nc: denotes ? no connection ? . 4. all unlisted pin numbers are user i/o ? s. 5. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. 84-pin plcc package pin number a1225xl function a1240xl function a3265dx function a1280xl function a32100dx function a32140dx function 2 clkb, i/o clkb, i/o clkb, i/o clkb, i/o clkb, i/o clkb, i/o 4 prb, i/o prb, i/o prb, i/o prb, i/o prb, i/o prb, i/o 5 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 6 gnd gnd gnd gnd gnd gnd 7 i/o i/o i/o i/o qclkc, i/o i/o 8 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 9 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 10 dclk, i/o dclk, i/o dclk, i/o dclk, i/o dclk, i/o dclk, i/o 12 mode (gnd) mode (gnd) mode (gnd) mode (gnd) mode (gnd) mode (gnd) 22 v cc v cc v cc v cc v cc v cc 23 v cc v cc v cc v cc v cc v cc 28 gnd gnd gnd gnd gnd gnd 34 i/o i/o i/o i/o tms, i/o tms, i/o 35 i/o i/o i/o i/o tdi, i/o tdi, i/o 36 i/o i/o i/o i/o i/o (wd) i/o (wd) 37 i/o i/o i/o i/o qclka, i/o i/o 38 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 39 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 43 v cc v cc v cc v cc v cc v cc 44 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 45 i/o i/o i/o i/o qclkb, i/o i/o (wd) 46 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 47 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 49 gnd gnd gnd gnd gnd gnd 50 i/o i/o i/o i/o i/o (wd) i/o (wd) 51 i/o i/o i/o i/o i/o (wd) i/o (wd) 52 i/o i/o i/o i/o sdo, tdo, i/o sdo, tdo, i/o 53 i/o i/o i/o i/o i/o i/o 62 i/o i/o i/o i/o tck, i/o tck, i/o 63 gnd gnd gnd gnd gnd gnd 64 v cc v cc v cc v cc v cc v cc 65 v cc v cc v cc v cc v cc v cc 70 gnd gnd gnd gnd gnd gnd 76 sdi, i/o sdi, i/o sdi, i/o sdi, i/o sdi, i/o sdi, i/o 78 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 79 i/o i/o i/o (wd) i/o i/o (wd) i/o (wd) 80 i/o i/o i/o (wd) i/o qclkd, i/o i/o (wd) 81 pra, i/o pra, i/o pra, i/o pra, i/o pra, i/o pra, i/o 83 clka, i/o clka, i/o clka, i/o clka, i/o clka, i/o clka, i/o 84 v cc v cc v cc v cc v cc v cc
integrator series fpgas: 1200xl and 3200dx families 58 v3.0 package pin assignments (continued) 100-pin pqfp package, 100-pin vqfp package (top view) 100-pin pqfp 1 100 1 100-pin vqfp 100
v3.0 59 integrator series fpgas: 1200xl and 3200dx families 100-pin pqfp package, 100-pin vqfp package pin number a1225xl- pq100 function a1225xl- vq100 function a1240xl- pq100 function a3265dx pq100 function 2 dclk, i/o mode (gnd) dclk, i/o dclk, i/o 4 mode (gnd) i/o mode (gnd) mode (gnd) 7 i/o gnd i/o i/o 9gndi/ogndgnd 14 i/o v cc i/o i/o 15 i/o v cc i/o i/o 16 v cc i/o v cc v cc 17 v cc i/o v cc v cc 20 i/o gnd i/o i/o 22 gnd i/o gnd gnd 32 i/o gnd i/o i/o 34 gnd i/o gnd gnd 35 i/o i/o i/o i/o (wd) 36 i/o i/o i/o i/o (wd) 37 i/o i/o i/o i/o (wd) 38 i/o v cc i/o i/o (wd) 40 v cc i/o v cc v cc 41 i/o i/o i/o i/o (wd) 42 i/o i/o i/o i/o (wd) 44 i/o gnd i/o i/o (wd) 45 i/o i/o i/o i/o (wd) 46 gnd i/o gnd gnd 47 i/o i/o i/o i/o (wd) 48 i/o i/o i/o i/o (wd) 50 i/o sdo, i/o i/o i/o 52 sdo, i/o i/o sdo, i/o sdo, i/o 55 i/o gnd i/o i/o 57 gnd i/o gnd gnd 62 i/o gnd i/o i/o 63 i/o v cc i/o i/o 64 gnd v cc gnd gnd 65 v cc v cc v cc v cc 66 v cc i/o v cc v cc 67 v cc i/o v cc v cc 70 i/o gnd i/o i/o 72 gnd i/o gnd gnd 77 i/o sdi, i/o i/o i/o 79 sdi, i/o i/o sdi, i/o sdi, i/o 81 i/o i/o i/o i/o (wd) 82 i/o gnd i/o i/o (wd) 83 i/o i/o i/o i/o (wd) 84 gnd i/o gnd gnd 85 i/o pra, i/o i/o i/o (wd) 86 i/o i/o i/o i/o (wd)
integrator series fpgas: 1200xl and 3200dx families 60 v3.0 notes: 1. nc: denotes ? no connection ? . 2. all unlisted pin numbers are user i/o ? s. 3. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. 4. i/o (wd): denotes i/o pin with an associated wide-decode module 87 pra, i/o clka, i/o pra, i/o pra, i/o 88 i/o v cc i/o i/o 89 clka, i/o i/o clka, i/o clka, i/o 90 v cc clkb, i/o v cc v cc 92 clkb, i/o prb, i/o clkb, i/o clkb, i/o 94 prb, i/o gnd prb, i/o prb, i/o 95 i/o i/o i/o i/o (wd) 96 gnd i/o gnd gnd 99 i/o i/o i/o i/o (wd) 100 i/o dclk, i/o i/o i/o (wd) 100-pin pqfp package, 100-pin vqfp package (continued) pin number a1225xl- pq100 function a1225xl- vq100 function a1240xl- pq100 function a3265dx pq100 function
v3.0 61 integrator series fpgas: 1200xl and 3200dx families package pin assignments (continued) 144-pin pqfp package (top view) 1 144 144-pin pqfp
integrator series fpgas: 1200xl and 3200dx families 62 v3.0 notes: 1. nc: denotes ? no connection ? . 2. all unlisted pin numbers are user i/o ? s. 3. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. 144-pin pqfp package pin number a1240xl function pin number a1240xl function 2 mode (gnd) 89 v cc 9gnd 90v cc 10 gnd 91 v cc 11 gnd 92 v cc 18 v cc 93 v cc 19 v cc 100 gnd 20 v cc 101 gnd 21 v cc 102 gnd 28 gnd 110 sdi, i/o 29 gnd 116 gnd 30 gnd 117 gnd 44 gnd 118 gnd 45 gnd 123 pra, i/o 46 gnd 125 clka, i/o 54 v cc 126 v cc 55 v cc 127 v cc 56 v cc 128 v cc 64 gnd 130 clkb, i/o 65 gnd 132 prb, i/o 79 gnd 136 gnd 80 gnd 137 gnd 81 gnd 138 gnd 88 gnd 144 dclk, i/o
v3.0 63 integrator series fpgas: 1200xl and 3200dx families package pin assignments (continued) 160-pin pqfp package (top view) notes: 1. i/o (wd): denotes i/o pin with an associated wide-decode module 2. wide-decode i/o (wd) can also be general-purpose user i/o. 3. nc denotes ? no connection ? . 4. all unlisted pin numbers are user i/o ? s. 5. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. 160 1 160-pin pqfp
integrator series fpgas: 1200xl and 3200dx families 64 v3.0 160-pin pqfp package pin number a3265dx function a1280xl function a32100dx function a32140dx function 2 dclk, i/o dclk, i/o dclk dclk, i/o 4 i/o i/o i/o (wd) i/o (wd) 5 i/o (wd) i/o i/o (wd) i/o (wd) 6v cc v cc v cc v cc 7 i/o (wd) i/o i/o i/o 11 gnd gnd gnd gnd 12 i/o i/o qclkc, i/o i/o 13 i/o (wd) i/o i/o (wd) i/o (wd) 14 i/o (wd) i/o i/o (wd) i/o (wd) 16 prb, i/o prb, i/o prb, i/o prb, i/o 18 clkb, i/o clkb, i/o clkb, i/o clkb, i/o 20 v cc v cc v cc v cc 21 clka, i/o clka, i/o clka, i/o clka, i/o 23 pra, i/o pra, i/o pra, i/o pra, i/o 24 i/o i/o i/o (wd) i/o (wd) 25 i/o (wd) i/o i/o (wd) i/o (wd) 26 i/o (wd) i/o i/o i/o 28 i/o i/o qclkd i/o 29 i/o (wd) i/o i/o (wd) i/o (wd) 30 gnd gnd gnd gnd 31 i/o (wd) i/o i/o (wd) i/o (wd) 33 i/o i/o nc i/o 34 i/o (wd) i/o nc i/o 35 v cc v cc v cc v cc 36 i/o (wd) i/o i/o (wd) i/o (wd) 37 i/o i/o i/o (wd) i/o (wd) 38 sdi, i/o sdi, i/o sdi, i/o sdi, i/o 40 gnd gnd gnd gnd 44 gnd gnd gnd gnd 49 gnd gnd gnd gnd 54 v cc v cc v cc v cc 57 v cc v cc v cc v cc 58 v cc v cc v cc v cc 59 gnd gnd gnd gnd 60 v cc v cc v cc v cc 61 gnd gnd gnd gnd 62 i/o i/o tck, i/o tck, i/o 64 gnd gnd gnd gnd 69 gnd gnd gnd gnd 80 gnd gnd gnd gnd 82 i/o i/o sdo, i/o sdo, tdo, i/o 83 i/o i/o i/o (wd) i/o (wd) 84 i/o i/o i/o (wd) i/o (wd) 86 v cc v cc v cc v cc 87 i/o (wd) i/o i/o i/o 88 i/o (wd) i/o i/o (wd) i/o (wd) 89 gnd gnd gnd gnd 90 i/o i/o i/o (wd) i/o
v3.0 65 integrator series fpgas: 1200xl and 3200dx families 91 i/o i/o qclkb, i/o i/o 92 i/o (wd) i/o i/o i/o 93 i/o (wd) i/o i/o i/o 95 i/o i/o i/o (wd) i/o 96 i/o (wd) i/o i/o (wd) i/o (wd) 97 i/o (wd) i/o i/o i/o 98 v cc v cc v cc v cc 99 gnd gnd gnd gnd 106 i/o (wd) i/o i/o (wd) i/o (wd) 107 i/o (wd) i/o i/o (wd) i/o (wd) 109 gnd gnd gnd gnd 110 i/o i/o qclka, i/o i/o 111 i/o (wd) i/o i/o i/o (wd) 112 i/o (wd) i/o i/o i/o (wd) 114 v cc v cc v cc v cc 115 i/o i/o i/o (wd) i/o (wd) 116 i/o i/o i/o (wd) i/o (wd) 118 i/o i/o tdi, i/o tdi, i/o 119 i/o i/o tms, i/o tms, i/o 120 gnd gnd gnd gnd 125 gnd gnd gnd gnd 130 gnd gnd gnd gnd 135 v cc v cc v cc v cc 138 v cc v cc v cc v cc 139 v cc v cc v cc v cc 140 gnd gnd gnd gnd 145 gnd gnd gnd gnd 150 v cc v cc v cc v cc 155 gnd gnd gnd gnd 159 mode (gnd) mode (gnd) mode (gnd) mode (gnd) 160 gnd gnd gnd gnd 160-pin pqfp package (continued) pin number a3265dx function a1280xl function a32100dx function a32140dx function
integrator series fpgas: 1200xl and 3200dx families 66 v3.0 package pin assignments (continued) 208-pin pqfp package, 208-pin rqfp package (top view) notes: 1. i/o (wd): denotes i/o pin with an associated wide-decode module. 2. wide-decode i/o (wd) can also be general purpose user i/o. 3. nc: denotes ? no connection ? . 4. all unlisted pin numbers are user i/o ? s. 5. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. 6. rqfp has an exposed circular metal heat sink on the top surface. 208-pin pqfp 208-pin rqfp 1 208
v3.0 67 integrator series fpgas: 1200xl and 3200dx families 208-pin pqfp package, 208-pin rqfp package pin number a1280xl function a32100dx function a32140dx function a32200dx- pq208 function a32200dx- rq208 function a32300dx function 1 gnd gnd gnd gnd i/o i/o 2nc v cc v cc v cc dclk, i/o dclk, i/o 3 mode (gnd) mode (gnd) mode (gnd) mode (gnd) i/o i/o 5 i/o i/o i/o i/o i/o (wd) i/o (wd) 6 i/o i/o i/o i/o i/o (wd) i/o (wd) 7 i/o i/o i/o i/o v cc v cc 9 nc nc i/o i/o i/o i/o 10 nc nc i/o i/o i/o i/o 11 nc nc i/o i/o i/o i/o 13 i/o i/o i/o i/o qclkc, i/o qclkc, i/o 15 i/o i/o i/o i/o i/o (wd) i/o (wd) 16 nc nc i/o i/o i/o (wd) i/o (wd) 17 v cc v cc v cc v cc i/o i/o 19 i/o i/o i/o i/o i/o (wd) i/o (wd) 20 i/o i/o i/o i/o i/o (wd) i/o (wd) 22 gnd gnd gnd gnd prb, i/o prb, i/o 24 i/o i/o i/o i/o clkb, i/o clkb, i/o 26 i/o i/o i/o i/o gnd gnd 27 gnd gnd gnd gnd v cc v cc 28 v cc v cc v cc v cc i/o i/o 29 v cc v cc v cc v cc clka, i/o clka, i/o 30 i/o i/o i/o i/o pra, i/o pra, i/o 32 v cc v cc v cc v cc i/o (wd) i/o (wd) 33 i/o i/o i/o i/o i/o (wd) i/o (wd) 38 i/o i/o i/o i/o qclkd, i/o qclkd, i/o 40 i/o i/o i/o i/o i/o (wd) i/o (wd) 41 nc nc i/o i/o i/o (wd) i/o (wd) 42 nc nc i/o i/o i/o i/o 43 nc nc i/o i/o i/o i/o 45 i/o i/o i/o i/o v cc v cc 47 i/o i/o i/o i/o i/o (wd) i/o (wd) 48 i/o i/o i/o i/o i/o (wd) i/o (wd) 50 nc nc i/o i/o sdi, i/o sdi, i/o 51 nc nc i/o i/o i/o i/o 52 gnd gnd gnd gnd gnd gnd 53 gnd gnd gnd gnd i/o i/o 54 i/o tms, i/o tms, i/o tms, i/o i/o i/o 55 i/o tdi, i/o tdi, i/o tdi, i/o i/o i/o 57 i/o i/o i/o (wd) i/o (wd) i/o i/o 58 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 59 i/o i/o (wd) i/o i/o gnd gnd 60 v cc v cc v cc v cc i/o i/o 61 nc i/o i/o i/o i/o i/o 62 nc i/o i/o i/o i/o i/o 65 i/o qclka, i/o i/o qclka, i/o i/o i/o 66 i/o i/o i/o (wd) i/o (wd) i/o i/o 67 nc nc i/o (wd) i/o (wd) i/o i/o 68 nc i/o i/o i/o i/o i/o 70 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 71 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 74 i/o i/o i/o i/o v cc v cc 77 i/o i/o i/o i/o v cc v cc 78 gnd gnd gnd gnd v cc v cc
integrator series fpgas: 1200xl and 3200dx families 68 v3.0 79 v cc v cc v cc v cc v cc v cc 80 nc v cc v cc v cc gnd gnd 81 i/o i/o i/o i/o tck, i/o tck, i/o 83 i/o i/o i/o i/o gnd gnd 85 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 86 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 89 nc i/o i/o i/o i/o i/o 90 nc i/o i/o i/o i/o i/o 91 i/o qclkb, i/o i/o qclkb, i/o i/o i/o 93 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 94 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 95 nc i/o i/o i/o i/o i/o 96 nc nc i/o i/o i/o i/o 97 nc nc i/o i/o i/o i/o 98 v cc v cc v cc v cc i/o i/o 100 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 101 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 103 i/o sdo, i/o sdo, tdo, i/o sdo, tdo, i/o v cc v cc 104 i/o i/o i/o i/o gnd gnd 105 gnd gnd gnd gnd i/o i/o 106 nc v cc v cc v cc sdo, tdo, i/o sdo, tdo, i/o 107 i/o i/o i/o i/o i/o (wd) i/o (wd) 108 i/o i/o i/o i/o i/o (wd) i/o (wd) 110 i/o i/o i/o i/o v cc v cc 112 nc nc i/o i/o i/o i/o 113 nc nc i/o i/o i/o i/o 114 nc nc i/o i/o i/o (wd) i/o (wd) 115 nc nc i/o i/o i/o (wd) i/o (wd) 117 i/o i/o i/o i/o qclkb, i/o qclkb, i/o 121 i/o i/o i/o i/o i/o (wd) i/o (wd) 122 i/o i/o i/o i/o i/o (wd) i/o (wd) 126 gnd gnd gnd gnd i/o i/o (wd) 127 i/o i/o i/o i/o i/o i/o (wd) 128 i/o tck, i/o tck, i/o tck, i/o i/o i/o 129 gnd gnd gnd gnd v cc v cc 130 v cc v cc v cc v cc gnd gnd 131 gnd gnd gnd gnd i/o i/o 132 v cc v cc v cc v cc i/o i/o 133 v cc v cc v cc v cc i/o i/o 136 v cc v cc v cc v cc i/o i/o 137 i/o i/o i/o i/o i/o (wd) i/o (wd) 138 i/o i/o i/o i/o i/o (wd) i/o (wd) 141 nc i/o i/o i/o i/o (wd) i/o (wd) 142 i/o i/o i/o i/o i/o (wd) i/o (wd) 144 i/o i/o i/o i/o qclka, i/o qclka, i/o 146 nc nc i/o i/o i/o i/o 147 nc nc i/o i/o i/o i/o 148 nc nc i/o i/o i/o i/o 149 nc nc i/o i/o v cc v cc 150 gnd gnd gnd gnd i/o i/o 151 i/o i/o i/o i/o i/o (wd) i/o (wd) 152 i/o i/o i/o i/o i/o (wd) i/o (wd) 154 i/o i/o i/o i/o tdi, i/o tdi, i/o 208-pin pqfp package, 208-pin rqfp package (continued) pin number a1280xl function a32100dx function a32140dx function a32200dx- pq208 function a32200dx- rq208 function a32300dx function
v3.0 69 integrator series fpgas: 1200xl and 3200dx families 155 i/o i/o i/o i/o tms, i/o tms, i/o 156 i/o i/o i/o i/o gnd gnd 157 gnd gnd gnd gnd v cc v cc 159 sdi, i/o sdi, i/o sdi, i/o sdi, i/o i/o i/o 161 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 162 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 164 v cc v cc v cc v cc i/o i/o 165 nc nc i/o i/o i/o i/o 166 nc nc i/o i/o i/o i/o 168 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 169 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 171 nc qclkd, i/o i/o qclkd, i/o i/o i/o 176 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 177 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 178 pra, i/o pra, i/o pra, i/o pra, i/o v cc v cc 180 clka, i/o clka, i/o clka, i/o clka, i/o i/o i/o 181 nc i/o i/o i/o v cc v cc 182 nc v cc v cc v cc v cc v cc 183 v cc v cc v cc v cc i/o i/o 184 gnd gnd gnd gnd i/o i/o 186 clkb, i/o clkb clkb, i/o clkb, i/o i/o i/o 187 i/o i/o i/o i/o gnd gnd 188 prb, i/o prb, i/o prb, i/o prb, i/o i/o i/o 190 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 191 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 193 nc i/o i/o i/o i/o i/o 194 nc nc i/o (wd) i/o (wd) i/o i/o 195 nc i/o i/o (wd) i/o (wd) i/o i/o 196 i/o qclkc, i/o i/o qclkc, i/o i/o i/o 197 nc nc i/o i/o i/o i/o 201 nc i/o i/o i/o i/o i/o 202 v cc v cc v cc v cc i/o i/o 203 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 204 i/o i/o (wd) i/o (wd) i/o (wd) i/o i/o 206 i/o i/o i/o i/o mode mode (gnd) 207 dclk, i/o dclk, i/o dclk, i/o dclk, i/o v cc v cc 208 i/o i/o i/o i/o gnd gnd 208-pin pqfp package, 208-pin rqfp package (continued) pin number a1280xl function a32100dx function a32140dx function a32200dx- pq208 function a32200dx- rq208 function a32300dx function
integrator series fpgas: 1200xl and 3200dx families 70 v3.0 package pin assignments (continued) 240-pin rqfp package (top view) notes: 1. i/o (wd): denotes i/o pin with an associated wide-decode module. 2. wide-decode i/o (wd) can also be general purpose user i/o. 3. nc: denotes ? no connection. ? 4. all unlisted pin numbers are user i/o ? s. 5. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. 6. rqfp has an exposed circular metal heat sink on the top surface. 240-pin rqfp exposed heatsink 1 240
v3.0 71 integrator series fpgas: 1200xl and 3200dx families 240-pin rqfp package pin number a32200dx function a32300dx function pin number a32200dx function a32300dx function 2 dclk, i/o dclk, i/o 120 gnd gnd 6 i/o (wd) i/o (wd) 121 gnd gnd 7 i/o (wd) i/o (wd) 123 sdo, tdo, i/o sdo, tdo, i/o 8v cc v cc 125 i/o (wd) i/o (wd) 15 qclkc, i/o qclkc, i/o 126 i/o (wd) i/o (wd) 17 i/o (wd) i/o (wd) 128 v cc v cc 18 i/o (wd) i/o (wd) 132 i/o (wd) i/o (wd) 21 i/o (wd) i/o (wd) 133 i/o (wd) i/o (wd) 22 i/o (wd) i/o (wd) 135 qclkb, i/o qclkb, i/o 24 prb, i/o prb, i/o 142 i/o (wd) i/o (wd) 26 clkb, i/o clkb, i/o 143 i/o (wd) i/o (wd) 28 gnd gnd 147 i/o i/o (wd) 29 v cc v cc 148 i/o i/o (wd) 30 v cc v cc 150 v cc v cc 32 clka, i/o clka, i/o 151 v cc v cc 33 i/o i/o (wd) 152 gnd gnd 34 pra, i/o pra, i/o 159 i/o (wd) i/o (wd) 37 i/o (wd) i/o (wd) 160 i/o (wd) i/o (wd) 38 i/o (wd) i/o (wd) 163 i/o (wd) i/o (wd) 45 qclkd, i/o qclkd, i/o 164 i/o (wd) i/o (wd) 47 i/o (wd) i/o (wd) 166 qclka, i/o qclka, i/o 48 i/o (wd) i/o (wd) 172 v cc v cc 52 v cc v cc 174 i/o (wd) i/o (wd) 54 i/o (wd) i/o (wd) 175 i/o (wd) i/o (wd) 55 i/o (wd) i/o (wd) 178 tdi, i/o tdi, i/o 57 sdi, i/o sdi, i/o 179 tms, i/o tms, i/o 59 v cc v cc 180 gnd gnd 60 gnd gnd 181 v cc v cc 61 gnd gnd 182 gnd gnd 71 v cc v cc 192 v cc v cc 85 v cc v cc 206 v cc v cc 88 v cc v cc 209 v cc v cc 89 v cc v cc 210 v cc v cc 90 v cc v cc 219 v cc v cc 91 gnd gnd 227 v cc v cc 92 tck, i/o tck, i/o 237 gnd gnd 94 gnd gnd 238 mode (gnd) mode (gnd) 108 v cc v cc 239 v cc v cc 118 v cc v cc 240 gnd gnd 119 gnd gnd
integrator series fpgas: 1200xl and 3200dx families 72 v3.0 package pin assignments (continued) 176-pin tqfp package (top view) notes: 1. i/o (wd): denotes i/o pin with an associated wide-decode module. 2. wide-decode i/o (wd) can also be general-purpose user i/o. 3. nc: denotes ? no connection. ? 4. all unlisted pin numbers are user i/o ? s. 5. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. 176-pin tqfp 176 1
v3.0 73 integrator series fpgas: 1200xl and 3200dx families 176-pin tqfp package pin number a1240xl function a3265dx function a1280xl function a32100dx function a32140dx function 1 gnd gnd gnd gnd gnd 2 mode mode mode mode mode 8ncncncnci/o 10 nc nc i/o i/o i/o 11 nc nc i/o i/o i/o 13 nc v cc v cc v cc v cc 18 gnd gnd gnd gnd gnd 19 nc i/o i/o i/o i/o 20 nc i/o i/o i/o i/o 22 nc i/o i/o i/o i/o 23 gnd gnd gnd gnd gnd 24 nc v cc v cc v cc v cc 25 v cc v cc v cc v cc v cc 26 nc i/o i/o i/o i/o 27 nc i/o i/o i/o i/o 28 v cc v cc v cc v cc v cc 29 nc nc i/o i/o i/o 33 nc nc nc nc i/o 37 nc nc i/o i/o i/o 38 nc nc nc nc i/o 45 gnd gnd gnd gnd gnd 46 i/o i/o i/o tms, i/o tms, i/o 47 i/o i/o i/o tdi, i/o tdi, i/o 48 i/o nc i/o i/o i/o 49 i/o i/o i/o i/o i/o (wd) 50 i/o i/o i/o i/o (wd) i/o (wd) 51 i/o i/o i/o i/o (wd) i/o 52 nc v cc v cc v cc v cc 54 nc i/o (wd) i/o i/o i/o 55 nc i/o (wd) i/o i/o i/o (wd) 56 i/o i/o i/o i/o i/o (wd) 57 nc nc nc qclka, i/o i/o 59 i/o i/o (wd) i/o i/o (wd) i/o (wd) 60 i/o i/o (wd) i/o i/o (wd) i/o (wd) 61 nc i/o i/o i/o i/o 64 nc i/o i/o i/o i/o 66 nc i/o i/o i/o i/o 67 gnd gnd gnd gnd gnd 68 v cc v cc v cc v cc v cc 69 i/o i/o (wd) i/o i/o i/o (wd) 70 i/o i/o (wd) i/o i/o i/o (wd) 72 i/o i/o i/o i/o (wd) i/o 73 i/o i/o (wd) i/o i/o (wd) i/o 74 nc nc i/o i/o i/o 75 i/o i/o (wd) i/o i/o i/o 76 i/o i/o i/o qclkb, i/o i/o 77 nc nc nc i/o i/o (wd) 78 nc nc i/o i/o (wd) i/o (wd) 79 i/o i/o i/o i/o (wd) i/o 80 nc i/o (wd) i/o nc i/o
integrator series fpgas: 1200xl and 3200dx families 74 v3.0 81 i/o i/o (wd) i/o i/o i/o 82 nc v cc v cc v cc v cc 84 i/o i/o i/o i/o (wd) i/o (wd) 85 i/o i/o i/o i/o (wd) i/o (wd) 86 nc nc i/o i/o i/o 87 i/o i/o i/o sdo, tdo, i/o sdo, tdo, i/o 89 gnd gnd gnd gnd gnd 96 nc nc i/o i/o i/o 97 nc i/o i/o i/o i/o 101ncncncnci/o 103 nc i/o i/o i/o i/o 106 gnd gnd gnd gnd gnd 107 nc i/o i/o i/o i/o 108 nc i/o i/o tck, i/o tck, i/o 109 gnd gnd gnd gnd gnd 110 v cc v cc v cc v cc v cc 111 gnd gnd gnd gnd gnd 112 v cc v cc v cc v cc v cc 113 v cc v cc v cc v cc v cc 114 nc i/o i/o i/o i/o 115 nc i/o i/o i/o i/o 116 nc v cc v cc v cc v cc 117 i/o nc i/o i/o i/o 121ncncnci/o i/o 124 nc nc i/o i/o i/o 125 nc nc i/o i/o i/o 126ncncncnci/o 133 gnd gnd gnd gnd gnd 135 sdi, i/o sdi, i/o sdi, i/o sdi, i/o sdi, i/o 136 nc nc i/o i/o i/o 137 i/o i/o i/o i/o (wd) i/o (wd) 138 i/o i/o i/o i/o (wd) i/o (wd) 139 i/o i/o (wd) i/o i/o i/o 140 nc v cc v cc v cc v cc 141 i/o i/o (wd) i/o i/o i/o 142 i/o i/o i/o i/o (wd) i/o 143 nc i/o i/o i/o (wd) i/o 144 nc i/o (wd) i/o i/o i/o (wd) 145ncncncnci/o (wd) 146 i/o i/o (wd) i/o qclkd, i/o i/o 147 nc i/o i/o i/o i/o 149 i/o i/o (wd) i/o i/o i/o 150 i/o i/o (wd) i/o i/o (wd) i/o (wd) 151 nc i/o i/o i/o (wd) i/o (wd) 152 pra, i/o pra, i/o pra, i/o pra, i/o pra, i/o 154 clka, i/o clka, i/o clka, i/o clka, i/o clka, i/o 155 v cc v cc v cc v cc v cc 156 gnd gnd gnd gnd gnd 158 clkb, i/o clkb, i/o clkb, i/o clkb, i/o clkb, i/o 160 prb, i/o prb, i/o prb, i/o prb, i/o prb, i/o 176-pin tqfp package (continued) pin number a1240xl function a3265dx function a1280xl function a32100dx function a32140dx function
v3.0 75 integrator series fpgas: 1200xl and 3200dx families 161 nc i/o i/o i/o (wd) i/o (wd) 162 i/o i/o (wd) i/o i/o (wd) i/o (wd) 163 i/o i/o (wd) i/o i/o i/o 164 i/o i/o i/o qclkc, i/o i/o 165ncncncnci/o (wd) 166 nc i/o i/o i/o i/o (wd) 168 nc i/o i/o i/o i/o 169 i/o i/o (wd) i/o i/o i/o 170 nc v cc v cc v cc v cc 171 i/o i/o (wd) i/o i/o (wd) i/o (wd) 172 i/o i/o i/o i/o (wd) i/o (wd) 173 nc nc i/o i/o i/o 175 dclk, i/o dclk, i/o dclk, i/o dclk, i/o dclk, i/o 176-pin tqfp package (continued) pin number a1240xl function a3265dx function a1280xl function a32100dx function a32140dx function
integrator series fpgas: 1200xl and 3200dx families 76 v3.0 package pin assignments (continued) 100-pin cpga (top view) signal pad number location pra or i/o 85 a7 prb or i/o 92 a4 mode 2 c2 sdi or i/o 77 c8 dclk or i/o 100 c3 clka or i/o 87 c6 clkb or i/o 90 d6 gnd 7, 20, 32, 44, 55, 70, 82, 94 e3, g3, j5, j7, g9, f11, d10, c7, c5 v cc 15, 38, 64, 88 f3, g1, k6, f9, f10, e11, b6 notes: 1. unused i/o pins are designated as outputs by als and are driven low. 2. all unassigned pins are available for use as i/os. 3. mode = gnd, except during device programming or debugging. 1 a 234567891011 b c d e f g h j k l a b c d e f g h j k l 100-pin cpga 1234567891011 orientation pin
v3.0 77 integrator series fpgas: 1200xl and 3200dx families package pin assignments (continued) 132-pin cpga (top view) signal pad number location pra or i/o 113 b8 prb or i/o 121 c6 mode 2 a1 sdi or i/o 101 b12 dclk or i/o 132 c3 clka or i/o 115 b7 clkb or i/o 119 b6 gnd 9, 10, 26, 27, 41, 58, 59, 73, 74, 92, 93, 107, 108, 125, 126 e3, f4, j2, j3, l5, l9, m9, k12, j11, h13, e12, e11, c9, b9, b5, c5 v cc 18, 19, 49, 50, 83, 84, 116, 117 g3, g2, g4, l7, k7, g10, g11, g12, g13, d7, c7 notes: 1. unused i/o pins are designated as outputs by als and are driven low. 2. all unassigned pins are available for use as i/os. 3. mode = gnd, except during device programming or debugging. 132-pin cpga a b c d e f g h j k l m n a b c d e f g h j k l m n orientation pin 1 2345678910111213 1 2345678910111213
integrator series fpgas: 1200xl and 3200dx families 78 v3.0 package pin assignments (continued) 176-pin cpga (top view) signal pad number location pra or i/o 152 c9 prb or i/o 160 d7 mode 2 c3 sdi or i/o 135 b14 dclk or i/o 175 b3 clka or i/o 154 a9 clkb or i/o 158 b8 gnd 1, 8, 18, 23, 33, 38, 45, 57, 67, 77, 89 101, 106, 111, 121, 126, 133, 145, 156, 165 d4, e4, g4, h4, k4, l4, m4, m6, m8, m10, m12 k12, j12, j13, h12, f12, e12, d12, d10, c8, d6 v cc 13, 24, 28, 52, 68, 82, 112, 116, 140, 155, 170 f4, h2, h3, j4, m5, n8, m11, j14, h13, h14, g12, d11, d8, d5 notes: 1. unused i/o pins are designated as outputs by als and are driven low. 2. all unassigned pins are available for use as i/os. 3. mode = gnd, except during device programming or debugging. 1 a 234567891011 b c d e f g h j k l 176-pin cpga 1234567891011 12 12 13 13 14 14 15 15 m n p r a b c d e f g h j k l m n p r
v3.0 79 integrator series fpgas: 1200xl and 3200dx families package pin assignments (continued) 84-pin cqfp notes: 1. unused i/o pins are designated as outputs by als and are driven low. 2. all unassigned pins are available for use as i/os. 3. mode = gnd, except during device programming or debugging. pin #1 index 1 84 84-pin cqfp
integrator series fpgas: 1200xl and 3200dx families 80 v3.0 84-pin cqfp package pin number a32100dx function pin number a32100dx function 1 gnd 51 tck, i/o 2 mode (gnd) 52 vks (gnd) 7v cc 53 v pp (v cc ) 10 gnd 55 v sv (v cc ) 11 v cc 56 v cc 12 v sv (v cc )59gnd 17 gnd 63 gnd 22 gnd 64 sdi 23 tms, i/o 65 i/o (wd) 24 tdi, i/o 66 i/o (wd) 25 i/o (wd) 67 i/o (wd) 26 i/o (wd) 68 i/o (wd) 28 qclka, i/o 69 qclkd, i/o 30 i/o (wd) 70 i/o (wd) 32 gnd 71 i/o (wd) 33 v cc 72 pra, i/o 34 i/o (wd) 73 clka, i/o 35 i/o (wd) 74 v cc 36 qclkb, i/o 76 clkb, i/o 37 i/o (wd) 77 prb, i/o 38 gnd 78 i/o (wd) 39 i/o (wd) 79 i/o (wd) 40 i/o (wd) 80 qclkc, i/o 41 i/o (wd) 81 gnd 42 sdo, i/o 82 i/o (wd) 43 gnd 83 i/o (wd) 50 gnd 84 dclk, i/o
v3.0 81 integrator series fpgas: 1200xl and 3200dx families package pin assignments (continued) 172-pin cqfp signal pad number clka or i/o 150 clkb or i/o 154 dclk or i/o 171 gnd 7, 17, 22, 32, 37, 55, 65, 75, 98, 103, 106, 118, 123, 141, 152, 161 mode 1 pra or i/o 148 prb or i/o 156 sdi or i/o 131 v cc 12, 23, 24, 27, 50, 66, 80, 107, 109, 110, 113, 136, 151, 166 notes: 1. unused i/o pins are designated as outputs by als and are driven low. 2. all unassigned pins are available for use as i/os. 3. mode = gnd, except during device programming or debugging. 172-pin cqfp pin #1 index 172 1
integrator series fpgas: 1200xl and 3200dx families 82 v3.0 list of changes the following table lists critical changes that were made in the current version of the document. data sheet categories in order to provide the latest information to designers, some data sheets are published before data has been fully characterized. these data sheets are marked as ? advanced ? or preliminary ? data sheets. the definition of these categories are as follows: advanced the data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but not for production. preliminary the data sheet contains information based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. unmarked (production) the data sheet contains information that is considered to be final. previous version changes in current version (v3.0) page unspecified because the changes in this data sheet are extensive and technical in nature due to the elimination of 32400dx product this should be viewed as a new document. please read it as you would a data sheet that is published for the first time. note that the package and mechanical drawings section has been eliminated from the data sheet and can now be found on the actel web site. all note that the package characteristics and mechanical drawings section has been eliminated from the data sheet. the mechanical drawings are now contained in a separate document, package characteristics and mechanical drawings, available on the actel web site.
v3.0 83 integrator series fpgas: 1200xl and 3200dx families
actel and the actel logo are registered trademarks of actel corporation. all other trademarks are the property of their owners. http://www.actel.com actel europe ltd. daneshill house, lutyens close basingstoke, hampshire rg24 8ag united kingdom tel: +44 (0)1256 305600 fax: +44 (0)1256 355420 actel corporation 955 east arques avenue sunnyvale, california 94086 usa tel: (408) 739-1010 fax: (408) 739-1540 actel asia-pacific exos ebisu bldg. 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan tel: +81 03-3445-7671 fax: +81 03-3445-7668 5172135-1/2.01

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